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Diffstat (limited to 'src/test/scala/firrtlTests/AttachSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/AttachSpec.scala | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index d1e07eae..3a67bf04 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -37,10 +37,9 @@ import firrtl.passes._ import firrtl.Parser.IgnoreInfo class InoutVerilog extends FirrtlFlatSpec { - def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo) private def executeTest(input: String, expected: Seq[String], compiler: Compiler) = { val writer = new StringWriter() - compiler.compile(parse(input), new AnnotationMap(Seq.empty), writer) + compiler.compile(CircuitState(parse(input), ChirrtlForm), writer) val lines = writer.toString().split("\n") map normalized expected foreach { e => lines should contain(e) @@ -176,7 +175,6 @@ class InoutVerilog extends FirrtlFlatSpec { } class AttachAnalogSpec extends FirrtlFlatSpec { - def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo) private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = { val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) => p.run(c) |