1 files changed, 30 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 6e5883d7..cf92ec1c 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -233,6 +233,36 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
        |endmodule""".stripMargin.split("\n") map normalized
     executeTest(input, check, compiler)
   }
+
+  it should "not error if not isinvalid" in {
+    val compiler = new VerilogCompiler
+    val input =
+     """circuit Attaching :
+        |  module Attaching :
+        |    output an: Analog<3>
+        |""".stripMargin
+    val check =
+     """module Attaching(
+       |  inout  [2:0] an
+       |);
+       |endmodule""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
+  it should "not error if isinvalid" in {
+    val compiler = new VerilogCompiler
+    val input =
+     """circuit Attaching :
+        |  module Attaching :
+        |    output an: Analog<3>
+        |    an is invalid
+        |""".stripMargin
+    val check =
+     """module Attaching(
+       |  inout  [2:0] an
+       |);
+       |endmodule""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
 }
 
 class AttachAnalogSpec extends FirrtlFlatSpec {