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Diffstat (limited to 'src/test/scala/firrtlTests/AttachSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/AttachSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index cf92ec1c..c9c609df 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -48,7 +48,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec { |); |endmodule |""".stripMargin.split("\n") map normalized - executeTest(input, check, compiler) + executeTest(input, check, compiler, Seq(dontDedup("A"), dontDedup("B"))) } it should "attach two instances" in { |