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Diffstat (limited to 'src/test/scala/firrtlTests/AttachSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/AttachSpec.scala | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index 5eed33bd..c29a7e43 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -12,14 +12,6 @@ import firrtl.passes._ import firrtl.Parser.IgnoreInfo class InoutVerilogSpec extends FirrtlFlatSpec { - private def executeTest(input: String, expected: Seq[String], compiler: Compiler) = { - val writer = new StringWriter() - compiler.compile(CircuitState(parse(input), ChirrtlForm), writer) - val lines = writer.toString().split("\n") map normalized - expected foreach { e => - lines should contain(e) - } - } behavior of "Analog" |