1 files changed, 46 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index 98d51ac8..ebc94cc8 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -319,6 +319,52 @@ class AsyncResetSpec extends FirrtlFlatSpec {
     )
   }
 
+  "Unassigned asyncronously reset registers" should "properly constantprop" in {
+    val result = compileBody(
+      s"""
+         |input clock : Clock
+         |input reset : AsyncReset
+         |output z : UInt<1>[4]
+         |wire literal : UInt<1>[2]
+         |literal[0] <= UInt<1>("h01")
+         |literal[1] <= UInt<1>("h01")
+         |wire complex_literal : UInt<1>[4]
+         |complex_literal[0] <= literal[0]
+         |complex_literal[1] <= literal[1]
+         |complex_literal[2] <= UInt<1>("h00")
+         |complex_literal[3] <= UInt<1>("h00")
+         |reg r : UInt<1>[4], clock with : (reset => (reset, complex_literal))
+         |z <= r""".stripMargin
+    )
+    result shouldNot containLine("always @(posedge clock or posedge reset) begin")
+  }
+
+  "Constantly assigned asynchronously reset registers" should "properly constantprop" in {
+    val result = compileBody(
+      s"""
+         |input clock : Clock
+         |input reset : AsyncReset
+         |output z : UInt<1>
+         |reg r : UInt<1>, clock with : (reset => (reset, r))
+         |r <= UInt(0)
+         |z <= r""".stripMargin
+    )
+    result shouldNot containLine("always @(posedge clock or posedge reset) begin")
+  }
+
+  "Constantly assigned and initialized asynchronously reset registers" should "properly constantprop" in {
+    val result = compileBody(
+      s"""
+         |input clock : Clock
+         |input reset : AsyncReset
+         |output z : UInt<1>
+         |reg r : UInt<1>, clock with : (reset => (reset, UInt(0)))
+         |r <= UInt(0)
+         |z <= r""".stripMargin
+    )
+    result shouldNot containLine("always @(posedge clock or posedge reset) begin")
+  }
+
   "AsyncReset registers" should "emit 'else' case for reset even for trivial valued registers" in {
     val withDontTouch = s"""
       |circuit m :
@@ -341,7 +387,6 @@ class AsyncResetSpec extends FirrtlFlatSpec {
      )
 
   }
-
 }
 
 class AsyncResetExecutionTest extends ExecutionTest("AsyncResetTester", "/features")