1 files changed, 16 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index 8ad397b3..ed90954b 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -231,6 +231,22 @@ class AsyncResetSpec extends FirrtlFlatSpec {
     result should containLine ("always @(posedge clock or posedge reset) begin")
   }
 
+  "CheckResets" should "NOT raise StackOverflow Exception on Combinational Loops (should be caught by firrtl.transforms.CheckCombLoops)" in {
+    an [firrtl.transforms.CheckCombLoops.CombLoopException] shouldBe thrownBy {
+      compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |wire x : UInt<1>
+        |wire y : UInt<2>
+        |x <= UInt<1>("h01")
+        |node ad = add(x, y)
+        |node adt = tail(ad, 1)
+        |y <= adt
+        |reg r : UInt, clock with : (reset => (reset, y))
+        |""".stripMargin
+      )
+    }
+  }
 
   "Every async reset reg" should "generate its own always block" in {
     val result = compileBody(s"""