1 files changed, 135 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index c1078a03..6fcb647a 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -3,7 +3,6 @@
 package firrtlTests
 
 import firrtl._
-import firrtl.ir._
 import FirrtlCheckers._
 
 class AsyncResetSpec extends FirrtlFlatSpec {
@@ -30,6 +29,25 @@ class AsyncResetSpec extends FirrtlFlatSpec {
     result should containLine ("always @(posedge clock or posedge reset) begin")
   }
 
+  it should "work in nested and flipped aggregates with regular and partial connect" in {
+    val result = compileBody(s"""
+      |output fizz : { flip foo : { a : AsyncReset, flip b: AsyncReset }[2], bar : { a : AsyncReset, flip b: AsyncReset }[2] }
+      |output buzz : { flip foo : { a : AsyncReset, flip b: AsyncReset }[2], bar : { a : AsyncReset, flip b: AsyncReset }[2] }
+      |fizz.bar <= fizz.foo
+      |buzz.bar <- buzz.foo
+      |""".stripMargin
+    )
+
+    result should containLine ("assign fizz_foo_0_b = fizz_bar_0_b;")
+    result should containLine ("assign fizz_foo_1_b = fizz_bar_1_b;")
+    result should containLine ("assign fizz_bar_0_a = fizz_foo_0_a;")
+    result should containLine ("assign fizz_bar_1_a = fizz_foo_1_a;")
+    result should containLine ("assign buzz_foo_0_b = buzz_bar_0_b;")
+    result should containLine ("assign buzz_foo_1_b = buzz_bar_1_b;")
+    result should containLine ("assign buzz_bar_0_a = buzz_foo_0_a;")
+    result should containLine ("assign buzz_bar_1_a = buzz_foo_1_a;")
+  }
+
   it should "support casting to other types" in {
     val result = compileBody(s"""
       |input a : AsyncReset
@@ -77,7 +95,7 @@ class AsyncResetSpec extends FirrtlFlatSpec {
   }
 
   "Non-literals" should "NOT be allowed as reset values for AsyncReset" in {
-    an [passes.CheckHighForm.NonLiteralAsyncResetValueException] shouldBe thrownBy {
+    an [checks.CheckResets.NonLiteralAsyncResetValueException] shouldBe thrownBy {
       compileBody(s"""
         |input clock : Clock
         |input reset : AsyncReset
@@ -91,6 +109,121 @@ class AsyncResetSpec extends FirrtlFlatSpec {
     }
   }
 
+  "Late non-literals connections" should "NOT be allowed as reset values for AsyncReset" in {
+    an [checks.CheckResets.NonLiteralAsyncResetValueException] shouldBe thrownBy {
+      compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<8>
+        |input y : UInt<8>
+        |output z : UInt<8>
+        |wire a : UInt<8>
+        |reg r : UInt<8>, clock with : (reset => (reset, a))
+        |a <= y
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    }
+  }
+
+  "Hidden Non-literals" should "NOT be allowed as reset values for AsyncReset" in {
+    an [checks.CheckResets.NonLiteralAsyncResetValueException] shouldBe thrownBy {
+      compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<1>[4]
+        |input y : UInt<1>
+        |output z : UInt<1>[4]
+        |wire literal : UInt<1>[4]
+        |literal[0] <= UInt<1>("h00")
+        |literal[1] <= y
+        |literal[2] <= UInt<1>("h00")
+        |literal[3] <= UInt<1>("h00")
+        |reg r : UInt<1>[4], clock with : (reset => (reset, literal))
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    }
+  }
+  "Wire connected to non-literal" should "NOT be allowed as reset values for AsyncReset" in {
+    an [checks.CheckResets.NonLiteralAsyncResetValueException] shouldBe thrownBy {
+      compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<1>
+        |input y : UInt<1>
+        |input cond : UInt<1>
+        |output z : UInt<1>
+        |wire w : UInt<1>
+        |w <= UInt(1)
+        |when cond :
+        |  w <= y
+        |reg r : UInt<1>, clock with : (reset => (reset, w))
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    }
+  }
+
+  "Complex literals" should "be allowed as reset values for AsyncReset" in {
+    val result = compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<1>[4]
+        |output z : UInt<1>[4]
+        |wire literal : UInt<1>[4]
+        |literal[0] <= UInt<1>("h00")
+        |literal[1] <= UInt<1>("h00")
+        |literal[2] <= UInt<1>("h00")
+        |literal[3] <= UInt<1>("h00")
+        |reg r : UInt<1>[4], clock with : (reset => (reset, literal))
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    result should containLine ("always @(posedge clock or posedge reset) begin")
+  }
+
+  "Complex literals of complex literals" should "be allowed as reset values for AsyncReset" in {
+    val result = compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<1>[4]
+        |output z : UInt<1>[4]
+        |wire literal : UInt<1>[2]
+        |literal[0] <= UInt<1>("h01")
+        |literal[1] <= UInt<1>("h01")
+        |wire complex_literal : UInt<1>[4]
+        |complex_literal[0] <= literal[0]
+        |complex_literal[1] <= literal[1]
+        |complex_literal[2] <= UInt<1>("h00")
+        |complex_literal[3] <= UInt<1>("h00")
+        |reg r : UInt<1>[4], clock with : (reset => (reset, complex_literal))
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    result should containLine ("always @(posedge clock or posedge reset) begin")
+  }
+  "Literals of bundle literals" should "be allowed as reset values for AsyncReset" in {
+    val result = compileBody(s"""
+        |input clock : Clock
+        |input reset : AsyncReset
+        |input x : UInt<1>[4]
+        |output z : UInt<1>[4]
+        |wire bundle : {a: UInt<1>, b: UInt<1>}
+        |bundle.a <= UInt<1>("h01")
+        |bundle.b <= UInt<1>("h01")
+        |wire complex_literal : UInt<1>[4]
+        |complex_literal[0] <= bundle.a
+        |complex_literal[1] <= bundle.b
+        |complex_literal[2] <= UInt<1>("h00")
+        |complex_literal[3] <= UInt<1>("h00")
+        |reg r : UInt<1>[4], clock with : (reset => (reset, complex_literal))
+        |r <= x
+        |z <= r""".stripMargin
+      )
+    result should containLine ("always @(posedge clock or posedge reset) begin")
+  }
+
 
   "Every async reset reg" should "generate its own always block" in {
     val result = compileBody(s"""