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-rw-r--r--src/test/scala/firrtlTests/AnnotationTests.scala76
1 files changed, 30 insertions, 46 deletions
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 03131165..4017503e 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -7,6 +7,7 @@ import java.io.{File, FileWriter}
import firrtl.annotations._
import firrtl._
import firrtl.FileUtils
+import firrtl.options.Dependency
import firrtl.transforms.OptimizableExtModuleAnnotation
import firrtl.passes.InlineAnnotation
import firrtl.passes.memlib.PinAnnotation
@@ -14,24 +15,6 @@ import firrtl.util.BackendCompilationUtilities
import firrtl.testutils._
import org.scalatest.matchers.should.Matchers
-/**
- * An example methodology for testing Firrtl annotations.
- */
-trait AnnotationSpec extends LowTransformSpec {
- // Dummy transform
- def transform = new ResolveAndCheck
-
- // Check if Annotation Exception is thrown
- override def failingexecute(input: String, annotations: Seq[Annotation]): Exception = {
- intercept[AnnotationException] {
- compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty)
- }
- }
- def execute(input: String, check: Annotation, annotations: Seq[Annotation]): Unit = {
- val cr = compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty)
- cr.annotations.toSeq should contain (check)
- }
-}
object AnnotationTests {
@@ -45,7 +28,7 @@ object AnnotationTests {
// Abstract but with lots of tests defined so that we can use the same tests
// for Legacy and newer Annotations
-abstract class AnnotationTests extends AnnotationSpec with Matchers {
+abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with MakeCompiler {
import AnnotationTests._
def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation
@@ -59,20 +42,22 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
| input b : UInt<1>
| node c = b""".stripMargin
val ta = anno("c", "")
- execute(input, ta, Seq(ta))
+ val r = compile(input, Seq(ta))
+ r.annotations.toSeq should contain (ta)
}
"Deleting annotations" should "create a DeletedAnnotation" in {
- val compiler = new VerilogCompiler
+ val transform = Dependency[DeletingTransform]
+ val compiler = makeVerilogCompiler(Seq(transform))
val input =
"""circuit Top :
| module Top :
| input in: UInt<3>
|""".stripMargin
- val transform = new DeletingTransform
- val tname = transform.name
+
+ val tname = transform.getName
val inlineAnn = InlineAnnotation(CircuitName("Top"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, Seq(inlineAnn)), Seq(transform))
+ val result = compiler.transform(CircuitState(parse(input), Seq(inlineAnn)))
result.annotations.last should matchPattern {
case DeletedAnnotation(`tname`, `inlineAnn`) =>
}
@@ -84,7 +69,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming" should "propagate in Lowering of memories" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
// Uncomment to help debugging failing tests
// Logger.setClassLogLevels(Map(compiler.getClass.getName -> LogLevel.Debug))
val input =
@@ -104,7 +89,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
|""".stripMargin
val annos = Seq(anno("m.r.data.b", "sub"), anno("m.r.data", "all"), anno("m", "mem"),
dontTouch("Top.m"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("m_a", "mem"))
resultAnno should contain (anno("m_b_0", "mem"))
@@ -118,7 +103,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
resultAnno should not contain (anno("r"))
}
"Renaming" should "propagate in RemoveChirrtl and Lowering of memories" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -128,7 +113,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
| read mport r = m[in], clk
|""".stripMargin
val annos = Seq(anno("r.b", "sub"), anno("r", "all"), anno("m", "mem"), dontTouch("Top.m"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("m_a", "mem"))
resultAnno should contain (anno("m_b_0", "mem"))
@@ -143,7 +128,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming" should "propagate in ZeroWidth" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -158,7 +143,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
|""".stripMargin
val annos = Seq(anno("zero"), anno("x.a"), anno("x.b"), anno("y[0]"), anno("y[1]"),
anno("y[2]"), dontTouch("Top.x"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("x_a"))
resultAnno should not contain (anno("zero"))
@@ -174,7 +159,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming subcomponents" should "propagate in Lowering" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -198,7 +183,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
anno("write.a"), anno("write.b[0]"), anno("write.b[1]"),
dontTouch("Top.r"), dontTouch("Top.w"), dontTouch("Top.mem")
)
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should not contain (anno("in.a"))
resultAnno should not contain (anno("in.b[0]"))
@@ -233,7 +218,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming components" should "expand in Lowering" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -248,7 +233,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
|""".stripMargin
val annos = Seq(anno("in"), anno("out"), anno("w"), anno("r"), dontTouch("Top.r"),
dontTouch("Top.w"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("in_a"))
resultAnno should contain (anno("in_b_0"))
@@ -265,7 +250,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming subcomponents that aren't leaves" should "expand in Lowering" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -281,7 +266,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
|""".stripMargin
val annos = Seq(anno("in.b"), anno("out.b"), anno("w.b"), anno("r.b"),
dontTouch("Top.r"), dontTouch("Top.w"))
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("in_b_0"))
resultAnno should contain (anno("in_b_1"))
@@ -294,7 +279,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming" should "track constprop + dce" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -310,7 +295,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
anno("out.a"), anno("out.b[0]"), anno("out.b[1]"),
anno("n.a"), anno("n.b[0]"), anno("n.b[1]")
)
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should not contain (anno("in.a"))
resultAnno should not contain (anno("in.b[0]"))
@@ -333,7 +318,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming" should "track deleted modules AND instances in dce" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Dead :
@@ -360,7 +345,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
anno("foo", mod = "Dead"), anno("bar", mod = "Dead"),
anno("foo", mod = "DeadExt"), anno("bar", mod = "DeadExt")
)
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
/* Uncomment to help debug
println(result.circuit.serialize)
result.annotations.foreach{ a =>
@@ -387,7 +372,6 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Renaming" should "track deduplication" in {
- val compiler = new VerilogCompiler
val input =
"""circuit Top :
| module Child :
@@ -410,7 +394,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
val annos = Seq(
anno("x", mod = "Child"), anno("y", mod = "Child_1"), manno("Child"), manno("Child_1")
)
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compile(input, annos)
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("x", mod = "Child"))
resultAnno should contain (anno("y", mod = "Child"))
@@ -426,7 +410,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
"Annotations on empty aggregates" should "be deleted" in {
- val compiler = new VerilogCompiler
+ val compiler = makeVerilogCompiler()
val input =
"""circuit Top :
| module Top :
@@ -442,7 +426,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
anno("x"), anno("y.bar"), anno("y.fizz"), anno("y.buzz"), anno("a"), anno("b"), anno("c"),
anno("c[0].d"), anno("c[1].d")
)
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+ val result = compiler.transform(CircuitState(parse(input), annos))
val resultAnno = result.annotations.toSeq
resultAnno should contain (anno("x_foo"))
resultAnno should not contain (anno("a"))
@@ -470,7 +454,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
}
}
-class JsonAnnotationTests extends AnnotationTests with BackendCompilationUtilities {
+class JsonAnnotationTests extends AnnotationTests {
// Helper annotations
case class SimpleAnno(target: ComponentName, value: String) extends
SingleTargetAnnotation[ComponentName] {
@@ -514,7 +498,7 @@ class JsonAnnotationTests extends AnnotationTests with BackendCompilationUtiliti
| output z : UInt<1>
| z <= x
| node y = x""".stripMargin
- val testDir = createTestDirectory(this.getClass.getSimpleName)
+ val testDir = BackendCompilationUtilities.createTestDirectory(this.getClass.getSimpleName)
val annoFile = new File(testDir, "anno.json")
annoFileText.foreach { text =>
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-07 03:49:13 +0000