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Diffstat (limited to 'src/test/scala/firrtl/testutils/FirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtl/testutils/FirrtlSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala index 1dc56b15..e14dc78c 100644 --- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala +++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala @@ -39,7 +39,7 @@ object RenameTop extends Transform with PreservesAll[Transform] { override val optionalPrerequisites = Seq(Dependency[RenameModules]) - override val dependents = Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter]) + override val optionalPrerequisiteOf = Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter]) def execute(state: CircuitState): CircuitState = { val c = state.circuit |