aboutsummaryrefslogtreecommitdiff
path: root/src/main
diff options
context:
space:
mode:
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/firrtl/IR.scala4
-rw-r--r--src/main/scala/firrtl/Parser.scala2
-rw-r--r--src/main/scala/firrtl/Passes.scala4
-rw-r--r--src/main/stanza/compilers.stanza2
-rw-r--r--src/main/stanza/firrtl-ir.stanza2
-rw-r--r--src/main/stanza/ir-parser.stanza4
-rw-r--r--src/main/stanza/ir-utils.stanza7
-rw-r--r--src/main/stanza/passes.stanza34
-rw-r--r--src/main/stanza/primop.stanza2
-rw-r--r--src/main/stanza/verilog.stanza55
10 files changed, 72 insertions, 44 deletions
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 1e7c4ced..3dbf3dae 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -9,6 +9,10 @@ package firrtl
import scala.collection.Seq
// Should this be defined elsewhere?
+/*
+Structure containing source locator information.
+Member of most Stmt case classes.
+*/
trait Info
case object NoInfo extends Info
case class FileInfo(file: String, line: Int, column: Int) extends Info {
diff --git a/src/main/scala/firrtl/Parser.scala b/src/main/scala/firrtl/Parser.scala
index 00cd110e..98864e92 100644
--- a/src/main/scala/firrtl/Parser.scala
+++ b/src/main/scala/firrtl/Parser.scala
@@ -22,7 +22,7 @@ object Parser
val tokens = new CommonTokenStream(lexer)
val parser = new FIRRTLParser(tokens)
- // FIXME Dangerous
+ // FIXME Dangerous (TODO)
parser.getInterpreter.setPredictionMode(PredictionMode.SLL)
// Concrete Syntax Tree
diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala
index f5691c45..5aa74630 100644
--- a/src/main/scala/firrtl/Passes.scala
+++ b/src/main/scala/firrtl/Passes.scala
@@ -36,9 +36,7 @@ object Passes {
* and passing an environment to all statements in pre-order
* traversal, and resolving types in expressions in post-
* order traversal.
- * Type propagation for primary ops are defined here.
- * Notable cases: LetRec requires updating environment before
- * resolving the subexpressions in its elements.
+ * Type propagation for primary ops are defined in Primops.scala.
* Type errors are not checked in this pass, as this is
* postponed for a later/earlier pass.
*/
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 4d12ddcb..88a4141a 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -62,6 +62,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
;ExpandIndexedConnects() ;W
InlineIndexed()
InferTypes() ;R
+ ResolveGenders() ;W
+ CheckTypes() ;R
CheckGenders() ;W
ExpandWhens() ;W
InferWidths() ;R
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 5bc1ea68..d3f60646 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -158,10 +158,12 @@ public defstruct Connect <: Stmt : ;LOW
public defstruct StopStmt <: Stmt : ;LOW
info: FileInfo with: (as-method => true)
ret: Int
+ clk: Expression
public defstruct PrintfStmt <: Stmt : ;LOW
info: FileInfo with: (as-method => true)
string: String
args: List<Expression>
+ clk: Expression
public defstruct EmptyStmt <: Stmt ;LOW
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index a4ca89f7..c4480afb 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -246,8 +246,8 @@ defsyntax firrtl :
stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,WRITE)
stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,INFER)
stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s, i,RDWR)
- stmt = (stop(?ret:#int)) : StopStmt(first-info(form),ret)
- stmt = (printf(?str:#string ?es:#exp ...)) : PrintfStmt(first-info(form),str,es)
+ stmt = (stop( ?clk:#exp!, ?ret:#int)) : StopStmt(first-info(form),ret,clk)
+ stmt = (printf( ?clk:#exp!, ?str:#string ?es:#exp ...)) : PrintfStmt(first-info(form),str,es,clk)
stmt = (?s:#stmt/when) : s
stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index dbcf3b73..9bcf1fd9 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -279,9 +279,9 @@ defmethod print (o:OutputStream, c:Stmt) :
(c:EmptyStmt) :
print(o, "skip")
(c:StopStmt) :
- print-all(o, ["stop(" ret(c) ")"])
+ print-all(o, ["stop(" clk(c) ", " ret(c) ")"])
(c:PrintfStmt) :
- print-all(o, ["printf("]) ;"
+ print-all(o, ["printf(" clk(c) ", " ]) ;"
print-all(o, join(List(escape(string(c)),args(c)), ", "))
print(o, ")")
@@ -376,7 +376,8 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
(c:Connect) : Connect(info(c),f(loc(c)), f(exp(c)))
(c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c)))
(c:OnReset) : OnReset(info(c),f(loc(c)),f(exp(c)))
- (c:PrintfStmt) : PrintfStmt(info(c),string(c),map(f,args(c)))
+ (c:PrintfStmt) : PrintfStmt(info(c),string(c),map(f,args(c)),f(clk(c)))
+ (c:StopStmt) : StopStmt(info(c),ret(c),f(clk(c)))
(c) : c
public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index e31b30a9..02323181 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -365,7 +365,7 @@ defn remove-special-chars (c:Circuit) :
(s:Connect) : Connect(info(s),rename-e(loc(s)),rename-e(exp(s)))
(s:EmptyStmt) : s
(s:StopStmt) : s
- (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s)))
+ (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s)),rename-e(clk(s)))
Circuit(info(c),modules*, rename(main(c))) where :
val modules* =
@@ -821,7 +821,7 @@ defn resolve-genders (c:Circuit) :
val alt* = resolve-stmt(alt(s))
Conditionally(info(s),pred*,conseq*,alt*)
(s:PrintfStmt) :
- PrintfStmt(info(s),string(s),map(resolve-expr{_,MALE},args(s)))
+ PrintfStmt(info(s),string(s),map(resolve-expr{_,MALE},args(s)),clk(s))
(s) : map(resolve-stmt,s)
defn resolve-expr (e:Expression,desired:Gender) -> Expression :
@@ -977,10 +977,10 @@ defn expand-expr (e:Expression) -> List<EF> :
if inst?(e) :
for f in fields(type(e) as BundleType) map-append :
for x in generate-entry(name(f),type(f)) map :
- EF(WSubfield(e,name(x),type(x),gender(e)),flip(f) * flip(x))
+ EF(WSubfield(e,name(x),type(x),gender(e) * flip(x)),flip(f) * flip(x))
else :
for x in generate-entry(name(e),type(e)) map :
- EF(WRef(name(x),type(x),kind(e),gender(e)), flip(x))
+ EF(WRef(name(x),type(x),kind(e),gender(e) * flip(x)), flip(x))
(e:WSubfield) :
val f = {_ as Field} $
for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e)
@@ -1002,8 +1002,13 @@ defn expand-expr (e:Expression) -> List<EF> :
;val v = exp(head(expand-expr(value(e))))
;list(EF(Pad(v,width(e),type(e)),DEFAULT))
(e:DoPrim) :
- val args = for x in args(e) map : exp(head(expand-expr(x)))
- list(EF(DoPrim(op(e),args,consts(e),type(e)),DEFAULT))
+ val vargs = Vector<Expression>()
+ val vflips = Vector<Flip>()
+ for x in args(e) do :
+ val r = head(expand-expr(x))
+ add(vargs,exp(r))
+ add(vflips,flip(r))
+ list(EF(DoPrim(op(e),to-list(vargs),consts(e),type(e)),DEFAULT))
(e) : list(EF(e,DEFAULT))
defn lower-ports (ports:List<Port>) -> List<Port> :
@@ -1134,7 +1139,7 @@ defn lower (body:Stmt) -> Stmt :
Conditionally(info(s),exp(head $ expand-expr(pred(s))),lower-stmt(conseq(s)),lower-stmt(alt(s)))
(s:PrintfStmt) :
val args* = for x in args(s) map : exp(head(expand-expr(x)))
- PrintfStmt(info(s),string(s),args*)
+ PrintfStmt(info(s),string(s),args*,clk(s))
(s:Begin|EmptyStmt|StopStmt) : map(lower-stmt,s)
lower-stmt(body)
@@ -1267,7 +1272,12 @@ defn inline-indexed-m (m:InModule) -> InModule :
val cond = Conditionally(info(s),eq,Connect(info(s),e,replace-ref),EmptyStmt())
add(stmts,map(inline-indexed-s,cond))
(s:DecToIndexer) :
- if (gender(replace-ref) != MALE) : error("Shouldn't be here")
+ if (gender(replace-ref) != MALE) :
+ println(gender(replace-ref))
+ println(replace-ref)
+ println(indexed-dec)
+ println(indexer)
+ error("Shouldn't be here")
val cnct = Connect(info(s),replace-ref,head(exps(s)))
add(stmts,map(inline-indexed-e,cnct))
;println-all(["exps: " exps(s)])
@@ -2089,7 +2099,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
add(v,WGeq(width!(type(l)),width!(type(e))))
Connect(info(s),l,e)
(s:PrintfStmt) :
- PrintfStmt(info(s),string(s),map(gen-constraints,args(s)))
+ PrintfStmt(info(s),string(s),map(gen-constraints,args(s)),gen-constraints(clk(s)))
(s:Conditionally) :
val p = gen-constraints(pred(s))
add(v,WGeq(width!(type(p)),LongWidth(1)))
@@ -2373,7 +2383,7 @@ defn split-exp (c:Circuit) :
(c:PrintfStmt) :
val args* = for x in args(c) map :
map(split-exp-e{_,false,info(c)},x)
- val conseq* = PrintfStmt(info(c),string(c),args*)
+ val conseq* = PrintfStmt(info(c),string(c),args*,clk(c))
add(v,Conditionally(info(s),pred*,conseq*,alt(s)))
(c:StopStmt) :
add(v,Conditionally(info(s),pred*,c,alt(s)))
@@ -2383,7 +2393,7 @@ defn split-exp (c:Circuit) :
(s:PrintfStmt) :
val args* = for x in args(s) map :
map(split-exp-e{_,false,info(s)},x)
- add(v,PrintfStmt(info(s),string(s),args*))
+ add(v,PrintfStmt(info(s),string(s),args*,clk(s)))
(s:DefNode) :
val exp* = map(split-exp-e{_,name(s),info(s)},value(s))
add(v,DefNode(info(s),name(s),exp*))
@@ -2543,7 +2553,7 @@ defn pad-widths-s (s:Stmt) -> Stmt :
val args* = for x in args(s) map :
val i = int-width!(type(x))
pad-widths-e(i,x)
- PrintfStmt(info(s),string(s),args*)
+ PrintfStmt(info(s),string(s),args*,clk(s))
(s:DefNode) :
val i = int-width!(type(value(s)))
val exp* = pad-widths-e(i,value(s))
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index c1a1bfd4..b285e0ee 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -73,7 +73,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
val w* = switch {op(e) == _} :
ADD-OP : PlusWidth(get-max(0,1),LongWidth(1))
SUB-OP : PlusWidth(get-max(0,1),LongWidth(1))
- MUL-OP : PlusWidth(get-max(0,1),get-max(0,1))
+ MUL-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1]))
DIV-OP :
match(type(args(e)[0]),type(args(e)[1])) :
(t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 5cf42323..b5196dac 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -139,7 +139,7 @@ defn emit (e:Expression) -> String :
if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " emit(args(e)[1])]
else : [emit-as-type(args(e)[0],type(e)) " >> " emit(args(e)[1])]
SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " consts(e)[0]]
- SHIFT-RIGHT-OP : [emit-as-type(args(e)[0],type(e)) "[" width!(type(args(e)[0])) - to-long(1) ":" consts(e)[0] "]"]
+ SHIFT-RIGHT-OP : [emit(args(e)[0]) "[" width!(type(args(e)[0])) - to-long(1) ":" consts(e)[0] "]"]
;if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " consts(e)[0]]
;else : [emit-as-type(args(e)[0],type(e)) " >> " consts(e)[0]]
NEG-OP : ["-{" emit-as-type(args(e)[0],type(e)) "}"]
@@ -152,8 +152,8 @@ defn emit (e:Expression) -> String :
BIT-OR-OP : [emit-as-type(args(e)[0],type(e)) " | " emit-as-type(args(e)[1],type(e))]
BIT-XOR-OP : [emit-as-type(args(e)[0],type(e)) " ^ " emit-as-type(args(e)[1],type(e))]
CONCAT-OP : ["{" emit-as-type(args(e)[0],type(e)) "," emit-as-type(args(e)[1],type(e)) "}"]
- BIT-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] "]"]
- BITS-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] ":" consts(e)[1] "]"]
+ BIT-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] "]"]
+ BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] ":" consts(e)[1] "]"]
BIT-AND-REDUCE-OP :
var v = emit-as-type(args(e)[0],type(e))
for x in tail(args(e)) do :
@@ -182,7 +182,7 @@ defn emit-module (m:InModule) :
val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups
val cons = HashTable<Symbol,Expression>(symbol-hash) ; all connections
val ens = HashTable<Symbol,Expression>(symbol-hash) ; all enables
- val simuls = Vector<Streamable>()
+ val simuls = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
defn build-table (s:Stmt) -> False :
match(s) :
(s:DefWire|DefPoison|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) :
@@ -195,19 +195,27 @@ defn emit-module (m:InModule) :
ens[n] = pred(s)
cons[n] = exp(conseq(s) as Connect)
(c:PrintfStmt) :
- add(simuls,["if(" emit(pred(s)) ") begin"])
- add(simuls,[" $fdisplay(32/'h80000002," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"])
- add(simuls,["end"])
+ val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+ add(my-clk-simuls,["if(" emit(pred(s)) ") begin"])
+ add(my-clk-simuls,[" $fwrite(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"])
+ add(my-clk-simuls,["end"])
+ simuls[get-name(clk(c))] = my-clk-simuls
(c:StopStmt) :
- add(simuls,["if(" emit(pred(s)) ") begin"])
- add(simuls,[" $fdisplay(32/'h80000002," ret(c) ");"])
- add(simuls,[" $finish;"])
- add(simuls,["end"])
+ val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+ add(my-clk-simuls,["if(" emit(pred(s)) ") begin"])
+ add(my-clk-simuls,[" $fdisplay(STDERR,\"" ret(c) "\");"])
+ add(my-clk-simuls,[" $finish;"])
+ add(my-clk-simuls,["end"])
+ simuls[get-name(clk(c))] = my-clk-simuls
(s:PrintfStmt) :
- add(simuls,["$fdisplay(32/'h80000002," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"])
+ val my-clk-simuls = get?(simuls,get-name(clk(s)),Vector<Streamable>())
+ add(my-clk-simuls,["$fwrite(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"])
+ simuls[get-name(clk(s))] = my-clk-simuls
(c:StopStmt) :
- add(simuls,["$fdisplay(32/'h80000002," ret(c) ");"])
- add(simuls,["$finish;"])
+ val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+ add(my-clk-simuls,["$fdisplay(STDERR,\"" ret(c) "\");"])
+ add(my-clk-simuls,["$finish;"])
+ simuls[get-name(clk(c))] = my-clk-simuls
(s:Connect) :
val n = get-name(loc(s))
cons[n] = exp(s)
@@ -313,6 +321,8 @@ defn emit-module (m:InModule) :
add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
if length(ports(m)) == 0 : print(");\n")
+ if length(simuls) != 0 : print-all([" integer STDERR = 32'h80000002;\n"])
+
for w in wires do :
print(" ")
println-all(w)
@@ -353,14 +363,15 @@ defn emit-module (m:InModule) :
println-all(u)
println(" end")
- if length(simuls) != 0 :
- println("`ifndef SYNTHESIS")
- println(" always @(*) begin")
- for x in simuls do :
- print(" ")
- println-all(x)
- println(" end")
- println("`endif")
+ for x in simuls do :
+ if length(value(x)) != 0 :
+ println("`ifndef SYNTHESIS")
+ println-all([" always @(posedge " key(x) ") begin"])
+ for u in value(x) do :
+ print(" ")
+ println-all(u)
+ println(" end")
+ println("`endif")
println("endmodule")
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-01 22:15:53 +0000