diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 5414053a..17cb9d50 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -554,7 +554,13 @@ class VerilogEmitter extends Emitter { val rmem_port = WSubAccess(mem,raddrx,s.data_type,UNKNOWNGENDER) assign(rdata,rmem_port) val wmem_port = WSubAccess(mem,waddrx,s.data_type,UNKNOWNGENDER) - update(wmem_port,datax,clk,AND(AND(enx,maskx),wmode)) + + val tempName = namespace.newTemp + val tempExp = AND(enx,maskx) + declare("wire", tempName, tpe(tempExp)) + val tempWRef = wref(tempName, tpe(tempExp)) + assign(tempWRef, tempExp) + update(wmem_port,datax,clk,AND(tempWRef,wmode)) } } case (s:Begin) => s map (build_streams) |