aboutsummaryrefslogtreecommitdiff
path: root/src/main/stanza
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/stanza')
-rw-r--r--src/main/stanza/passes.stanza15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index cb4607b8..e9abaf74 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1844,11 +1844,16 @@ defn split-exp (m:InModule) -> InModule :
if i > 0 : split(e)
else : e
(e) : e
- match(map(split-exp-e{_,0},s)) :
+ match(s) :
(s:Begin) : map(split-exp-s,s)
- (s) :
- add(v,s)
- s
+ (s:Print) :
+ val s* = map(split-exp-e{_,1},s)
+ add(v,s*)
+ s*
+ (s) :
+ val s* = map(split-exp-e{_,0},s)
+ add(v,s*)
+ s*
split-exp-s(body(m))
InModule(info(m),name(m),ports(m),Begin(to-list(v)))
@@ -2696,7 +2701,7 @@ defn emit-verilog (m:InModule) -> Module :
defn stop (ret:Int) -> Streamable :
["$fdisplay(32'h80000002,\"" ret "\");$finish;"]
defn printf (str:String,args:List<Expression>) -> Streamable :
- val str* = join(List(escape(str),map(escape,map(to-string,args))),",")
+ val str* = join(List(escape(str),args),",")
["$fwrite(32'h80000002," str* ");"]
defn delay (e:Expression, n:Int, clk:Expression) -> Expression :
var e* = e