diff options
Diffstat (limited to 'src/main/stanza/verilog.stanza')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 50ea1fc1..96778469 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -80,7 +80,8 @@ defn emit (e:Expression) -> String : val x = args(e)[0] val w = width!(type(x)) val diff = consts(e)[0] - w - ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"] + if w == 0 : [ emit(x) ] + else : ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"] AS-UINT-OP : ["$unsigned(" emit(args(e)[0]) ")"] AS-SINT-OP : @@ -100,7 +101,7 @@ defn emit (e:Expression) -> String : BIT-XOR-OP : [emit(args(e)[0]) " ^ " emit(args(e)[1])] CONCAT-OP : ["{" emit(args(e)[0]) "," emit(args(e)[1]) "}"] BIT-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] "]"] - BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[1] ":" consts(e)[0] "]"] + BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] ":" consts(e)[1] "]"] BIT-AND-REDUCE-OP : var v = emit(args(e)[0]) for x in tail(args(e)) do : @@ -161,14 +162,9 @@ defn emit-module (m:InModule) : add(inst-ports[name(s)], ["." name(f) "( " n* " )"]) (s:DefMemory) : val vtype = type(s) as VectorType - if seq?(s) : - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"]) - else : - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"]) + add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) + add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) + add(inits,[" " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) |