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Diffstat (limited to 'src/main/stanza/verilog.stanza')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 23591f45..29112271 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -249,6 +249,7 @@ defn emit-module (m:InModule) : OUTPUT : print-all([port-indent "output " get-width(type(p)) " " name(p) end]) add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) + if length(ports(m)) == 0 : print(");\n") for w in wires do : print(" ") |