diff options
Diffstat (limited to 'src/main/stanza/primop.stanza')
| -rw-r--r-- | src/main/stanza/primop.stanza | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 14589135..e88a6b8e 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -248,12 +248,12 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim : BIT-XOR-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u()) public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : - defn all-equal (ls:List<Expression>) -> Width : - if length(ls) == 1 : width!(ls[0]) + defn all-equal (ls:List<Width>) -> Width : + if length(ls) == 1 : (ls[0]) else : - val m = MaxWidth(map(width!,ls)) + val m = MaxWidth(ls) for (l in ls) do : - add(v,WGeq(width!(l),m)) + add(v,WGeq(l,m)) m ;defn new-width (w:Width) -> Width: ; val w* = VarWidth(gensym(`w)) @@ -275,9 +275,11 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : val all-args-not-equal = list(MUX-UU-OP,MUX-SS-OP,CONCAT-OP) ;val consts-gte-args = list(PAD-U-OP,PAD-S-OP) + + val w-var = VarWidth(gensym(`w)) val w* = if not contains?(all-args-not-equal,op(e)) : - val max-args-w = all-equal(args(e)) + val max-args-w = all-equal(map(width!,args(e))) switch {op(e) == _} : ADD-UU-OP : PlusWidth(max-args-w,IntWidth(1)) ADD-US-OP : PlusWidth(max-args-w,IntWidth(1)) @@ -327,34 +329,36 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : PAD-S-OP : IntWidth(consts(e)[0]) NEG-U-OP : IntWidth(1) NEG-S-OP : IntWidth(1) - AS-UINT-U-OP : max-args-w - AS-UINT-S-OP : max-args-w - AS-SINT-U-OP : max-args-w - AS-SINT-S-OP : max-args-w SHIFT-LEFT-U-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-LEFT-S-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-U-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-S-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) CONVERT-U-OP : PlusWidth(max-args-w,IntWidth(1)) CONVERT-S-OP : max-args-w - BIT-NOT-OP : max-args-w - BIT-AND-OP : max-args-w - BIT-OR-OP : max-args-w - BIT-XOR-OP : max-args-w BIT-SELECT-OP : IntWidth(1) BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) else : switch {op(e) == _} : MUX-UU-OP : add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(tail(args(e))) + all-equal(List(w-var,tail(map(width!,args(e))))) MUX-SS-OP : add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(tail(args(e))) + all-equal(List(w-var,tail(map(width!,args(e))))) CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) + BIT-NOT-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) - val w-var = VarWidth(gensym(`w)) add(v,WGeq(w-var,w*)) match(type(e)) : (t:UIntType) : UIntType(w-var) |