diff options
Diffstat (limited to 'src/main/stanza/passes.stanza')
| -rw-r--r-- | src/main/stanza/passes.stanza | 376 |
1 files changed, 245 insertions, 131 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index b6926a7b..80035325 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -9,7 +9,7 @@ defpackage firrtl/passes : ;============== Pass List ================ public val standard-passes = to-list $ [ - CheckHighForm() + CheckHighForm(expand-delin) TempElimination() ToWorkingIR() MakeExplicitReset() @@ -85,6 +85,11 @@ defstruct ConnectFromIndexed <: Stmt : ;================ WORKING IR UTILS ========================= +;defmethod equal? (f1:Flip, f2:Flip) -> True|False : +; switch fn ([x,y]) : f1 == x and f2 == y : +; [DEFAULT,DEFAULT] : true +; [REVERSE,REVERSE] : true +; else : false defn plus (g1:Gender,g2:Gender) -> Gender : switch fn ([x,y]) : g1 == x and g2 == y : @@ -304,7 +309,9 @@ defn temp-elimination (c:Circuit) : Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : - Module(info(m),name(m), ports(m), temp-elim-s(body(m))) + match(m) : + (m:InModule) : InModule(info(m),name(m), ports(m), temp-elim-s(body(m))) + (m:ExModule) : m ;================= Bring to Working IR ======================== ; Returns a new Circuit with Refs, Subfields, Indexes and DefAccessors @@ -330,7 +337,9 @@ defn to-working-ir (c:Circuit) : Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : - Module(info(m),name(m), ports(m), to-stmt(body(m))) + match(m) : + (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m))) + (m:ExModule) : m ;=============== MAKE EXPLICIT RESET ======================= ; All modules have an implicit reset signal - however, the @@ -367,8 +376,11 @@ defn make-explicit-reset (c:Circuit) : var ports! = ports(m) if not contains?(explicit-reset,name(m)) : ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1))))) - val body! = route-reset(body(m)) - Module(info(m),name(m),ports!,body!) + match(m) : + (m:InModule) : + val body! = route-reset(body(m)) + InModule(info(m),name(m),ports!,body!) + (m:ExModule) : ExModule(info(m),name(m),ports!) defn make-explicit-reset (m:Module, c:Circuit) -> Module : val explicit-reset = find-explicit(c) @@ -417,15 +429,20 @@ defn resolve-kinds (c:Circuit) : kinds[name(m)] = ModuleKind() for p in ports(m) do : kinds[name(p)] = PortKind() - find-stmt(body(m)) + match(m) : + (m:InModule) : find-stmt(body(m)) + (m:ExModule) : false defn resolve-kinds (m:Module, c:Circuit) -> Module : val kinds = HashTable<Symbol,Kind>(symbol-hash) for m in modules(c) do : kinds[name(m)] = ModuleKind() find(m,kinds) - val body! = resolve(body(m),kinds) - Module(info(m),name(m),ports(m),body!) + match(m) : + (m:InModule) : + val body! = resolve(body(m),kinds) + InModule(info(m),name(m),ports(m),body!) + (m:ExModule) : ExModule(info(m),name(m),ports(m)) Circuit(info(c),modules*, main(c)) where : val modules* = @@ -504,15 +521,18 @@ defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt List<KeyValue< val [s*,l*] = infer-types(conseq(s),l) val [s**,l**] = infer-types(alt(s),l) [Conditionally(info(s),pred(s),s*,s**),l] - (s:Connect|OnReset|EmptyStmt) : [s,l] + (s:Connect|BulkConnect|OnReset|EmptyStmt) : [s,l] defn infer-types (m:Module, l:List<KeyValue<Symbol,Type>>) -> Module : val ptypes = for p in ports(m) map : name(p) => type(p) println-all-debug(append(ptypes,l)) - val [s,l*] = infer-types(body(m),append(ptypes, l)) - Module(info(m),name(m),ports(m),s) + match(m) : + (m:InModule) : + val [s,l*] = infer-types(body(m),append(ptypes, l)) + InModule(info(m),name(m),ports(m),s) + (m:ExModule) : m defn infer-types (c:Circuit) -> Circuit : val l = @@ -565,8 +585,11 @@ defn resolve-genders (c:Circuit) : var done? = true defn resolve-iter (m:Module) -> Module : - val body* = resolve-stmt(body(m)) - Module(info(m),name(m),ports(m),body*) + match(m) : + (m:InModule) : + val body* = resolve-stmt(body(m)) + InModule(info(m),name(m),ports(m),body*) + (m:ExModule) : m defn get-gender (n:Symbol,g:Gender) -> Gender : defn force-gender (n:Symbol,g:Gender) -> Gender : @@ -607,6 +630,8 @@ defn resolve-genders (c:Circuit) : WDefAccessor(info(s),name(s),source*,index*,gender*) (s:Connect) : Connect(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) + (s:BulkConnect) : + BulkConnect(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) (s:OnReset) : OnReset(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) (s:Conditionally) : @@ -696,7 +721,9 @@ defn expand-accessors (c:Circuit) : Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : - Module(info(m),name(m),ports(m),expand-stmt(body(m))) + match(m) : + (m:InModule) : InModule(info(m),name(m),ports(m),expand-stmt(body(m))) + (m:ExModule) : m ;;=============== LOWERING TO GROUND TYPES ============================= ; All non-ground (elevated) types (Vectors, Bundles) are expanded out to @@ -742,9 +769,8 @@ defn index-of-elem (t:BundleType, s:Symbol) -> Int : else : sum = sum + num-elems(type(f)) error("Shouldn't be here") - defn generate-entry (n:Symbol,t:Type) -> List<NTF> : - defn uniquify (n*:Symbol) -> Symbol : symbol-join([n "_" n*]) + defn uniquify (n*:Symbol) -> Symbol : symbol-join([n expand-delin n*]) match(t) : (t:BundleType) : for f in fields(t) map-append : @@ -840,7 +866,7 @@ defn lower (body:Stmt) -> Stmt : DefNode(info(s),name(s),exp(x)) (s:DefMemory) : Begin $ for x in generate-entry(name(s),type(type(s))) map : - DefMemory(info(s),name(x),VectorType(type(x),size(s))) + DefMemory(info(s),name(x),VectorType(type(x),size(s)), seq?(s)) (s:WDefAccessor) : val ls = generate-entry(name(s),type(s)) val rs = generate-entry(name(source(s) as WRef),type(s)) @@ -863,6 +889,28 @@ defn lower (body:Stmt) -> Stmt : [MALE,FEMALE] : if s typeof Connect : Connect(info(s),r*,l*) else : OnReset(info(s),r*,l*) + (s:BulkConnect) : + val ls-fake = generate-entry(`null,type(loc(s))) + val rs-fake = generate-entry(`null,type(exp(s))) + val ls = expand-expr(loc(s)) + val rs = expand-expr(exp(s)) + val ls* = Vector<EF>() + val rs* = Vector<EF>() + for (l-fake in ls-fake,l in ls) do : + for (r-fake in rs-fake, r in rs) do : + if name(l-fake) == name(r-fake) and flip(l-fake) == flip(r-fake) and type(l-fake) == type(r-fake) : + add(ls*,l) + add(rs*,r) + Begin $ for (l in to-list(ls*), r in to-list(rs*)) map : + val lgender = FEMALE * flip(l) + val rgender = MALE * flip(r) + val l* = set-gender(exp(l),lgender,flip(l)) + val r* = set-gender(exp(r),rgender,flip(r)) + println-all-debug(["Left: " l " with Gender: " lgender]) + println-all-debug(["Right: " r " with Gender: " rgender]) + switch fn ([x,y]) : lgender == x and rgender == y : + [FEMALE,MALE] : Connect(info(s),l*,r*) + [MALE,FEMALE] : Connect(info(s),r*,l*) (s:ConnectFromIndexed) : Begin(ls) where : val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash) for e in exps(s) do : @@ -908,9 +956,13 @@ defn lower (body:Stmt) -> Stmt : lower-stmt(body) defn lower-module (c:Circuit,m:Module) -> Module : - Module(info(m),name(m),ports*,body*) where : - val body* = lower(body(m)) - val ports* = lower-ports(ports(m)) + val ports* = lower-ports(ports(m)) + match(m) : + (m:InModule) : + val body* = lower(body(m)) + InModule(info(m),name(m),ports*,body*) + (m:ExModule) : + ExModule(info(m),name(m),ports*) defn lower-to-ground (c:Circuit) -> Circuit : Circuit(info(c),modules*, main(c)) where : @@ -928,20 +980,20 @@ public defmethod pass (b:ExpandIndexedConnects) -> (Circuit -> Circuit) : expand public defmethod name (b:ExpandIndexedConnects) -> String : "Expand Indexed Connects" public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexed-connects" -defn expand-connect-indexed-stmt (s: Stmt) -> Stmt : +defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt : defn equality (e1:Expression,e2:Expression) -> Expression : DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth())) defn get-name (e:Expression) -> Symbol : match(e) : - (e:WRef) : symbol-join([name(e) `__]) - (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) `__]) - (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) `__]) + (e:WRef) : symbol-join([name(e) gen-delin]) + (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) gen-delin]) + (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) gen-delin]) (e) : `T match(s) : (s:ConnectToIndexed) : Begin $ if length(locs(s)) == 0 : list(EmptyStmt()) else : - val ref = WRef(firrtl-gensym(get-name(exp(s))),type(index(s)),NodeKind(),UNKNOWN-GENDER) + val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER) append( list(DefNode(info(s),name(ref),index(s))) to-list $ @@ -955,7 +1007,7 @@ defn expand-connect-indexed-stmt (s: Stmt) -> Stmt : (s:ConnectFromIndexed) : Begin $ if length(exps(s)) == 0 : list(EmptyStmt()) else : - val ref = WRef(firrtl-gensym(get-name(loc(s))),type(index(s)),NodeKind(),UNKNOWN-GENDER) + val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER) append( list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s))) to-list $ @@ -966,10 +1018,14 @@ defn expand-connect-indexed-stmt (s: Stmt) -> Stmt : EmptyStmt() ) ) - (s) : map(expand-connect-indexed-stmt,s) + (s) : map(expand-connect-indexed-stmt{_,sh},s) defn expand-connect-indexed (m: Module) -> Module : - Module(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m))) + match(m) : + (m:InModule) : + val sh = get-sym-hash(m) + InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh)) + (m:ExModule) : m defn expand-connect-indexed (c: Circuit) -> Circuit : Circuit(info(c),modules*, main(c)) where : @@ -1173,63 +1229,49 @@ defn expand-whens (ports:List<Port>, table:HashTable<Symbol,SymbolicValue>,cons: for p in ports do : if direction(p) == OUTPUT : val ref = WRef(name(p),type(p),PortKind(),FEMALE) - add{cons,_} $ - if has-nul?(table[name(p)]) : - println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error - EmptyStmt() - else : Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression) + if has-nul?(table[name(p)]) : + println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error + else : add{cons,_} $ Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression) defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stmt>,cons:Vector<Stmt>) -> Stmt : match(map(expand-whens{_,table,decs,cons},s)) : (s:DefNode|DefMemory) : add(decs,s) (s:DefWire) : add(decs,s) - add{cons,_} $ { - val ref = WRef(name(s),type(s),NodeKind(),FEMALE) - if has-nul?(table[name(s)]) : - println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error - EmptyStmt() - else : Connect(info(s),ref,to-exp(table[name(s)]) as Expression) - }() + val ref = WRef(name(s),type(s),NodeKind(),FEMALE) + if has-nul?(table[name(s)]) : + println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error + else : add{cons,_} $ Connect(info(s),ref,to-exp(table[name(s)]) as Expression) (s:DefRegister) : - ;add(decs,DefWire(info(s),name(s),type(s))) - ;add{cons,_} $ { - ; val ref = WRef(name(s),type(s),RegKind(),FEMALE) - ; val e = to-exp(table[name(s)]) - ; match(e) : - ; (e:False) : EmptyStmt() - ; (e:Expression) : Connect(info(s),ref,Register(type(s),e, to-exp(optimize $ get-write-enable(table[name(s)])) as Expression)) - ;}() val e = to-exp(table[name(s)]) - add{cons,_} $ { - match(e) : - (e:False) : EmptyStmt() - (e:Expression) : DefNode(info(s),name(s),Register(type(s),e,to-exp(optimize $ get-write-enable(table[name(s)])) as Expression)) - }() + match(e) : + (e:Expression) : + add{decs,_} $ DefWire(info(s),name(s),type(s)) + val ref = WRef(name(s),type(s),NodeKind(),FEMALE) + add{cons,_} $ Connect(info(s),ref,Register(type(s),e,to-exp(optimize $ get-write-enable(table[name(s)])) as Expression)) + (e:False) : false (s:WDefAccessor) : val t = type(type(source(s)) as VectorType) val n = name(s) - add{cons,_} $ { switch {_ == gender(s)} : MALE : - Begin $ list $ DefNode(info(s),n,ReadPort(source(s),index(s),t,get-read-enable(n,table))) + add{decs,_} $ DefWire(info(s),n,t) + val ref = WRef(n,t,WriteAccessorKind(),FEMALE) + add{cons,_} $ Connect(info(s),ref,ReadPort(source(s),index(s),t,get-read-enable(n,table))) FEMALE : add(decs,DefWire(info(s),n,t)) - val ref = WRef(n,t,WriteAccessorKind(),FEMALE) + val ref = WRef(n,t,WriteAccessorKind(),MALE) + val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression + val wp = WritePort(source(s),index(s),t,enable as Expression) val e = to-exp(table[n]) - val s* = match(e) : + add{cons,_} $ Connect(info(s),wp,ref) + match(e) : (e:False) : println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error - EmptyStmt() (e:Expression) : - Connect(info(s),ref,e) - val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression - val wp = WritePort(source(s),index(s),t,enable as Expression) - Begin $ list(Connect(info(s),wp,ref),s*) - }() + add{cons,_} $ Connect(info(s),ref,e) (s:DefInstance) : add(decs,s) - add{cons,_} $ Begin $ for f in fields(type(module(s)) as BundleType) map : if flip(f) == REVERSE : val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs @@ -1239,9 +1281,7 @@ defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stm val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) if has-nul?(table[n]) : println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error - EmptyStmt() - else : Connect(info(s),sref,to-exp(table[n]) as Expression) - else : EmptyStmt() + else : add{cons,_} $ Connect(info(s),sref,to-exp(table[n]) as Expression) (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false s @@ -1347,34 +1387,37 @@ defn build-tables (s:Stmt, (s:DefMemory|DefNode|EmptyStmt) : false defn expand-whens (m:Module) -> Module : - val assign = HashTable<Symbol,SymbolicValue>(symbol-hash) - val resets = HashTable<Symbol,SymbolicValue>(symbol-hash) - val flattn = HashTable<Symbol,True|False>(symbol-hash) - - for p in ports(m) do : - if direction(p) == OUTPUT : - assign[name(p)] = SVNul() - flattn[name(p)] = false - - build-tables(body(m),assign,resets,flattn) - for x in assign do : assign[key(x)] = optimize(value(x)) - for x in resets do : resets[key(x)] = optimize(value(x)) - ;val enables = get-enables(assign,kinds) - ;for x in enables do : enables[key(x)] = optimize(value(x)) - - println-debug("====== Assigns ======") - for x in assign do : println-debug(x) - println-debug("====== Resets ======") - for x in resets do : println-debug(x) - - val table = merge-resets(assign,resets) - println-debug("====== Table ======") - for x in table do : println-debug(x) - val decs = Vector<Stmt>() - val cons = Vector<Stmt>() - expand-whens(ports(m),table,cons) - expand-whens(body(m),table,decs,cons) - Module(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) + match(m) : + (m:ExModule) : m + (m:InModule) : + val assign = HashTable<Symbol,SymbolicValue>(symbol-hash) + val resets = HashTable<Symbol,SymbolicValue>(symbol-hash) + val flattn = HashTable<Symbol,True|False>(symbol-hash) + + for p in ports(m) do : + if direction(p) == OUTPUT : + assign[name(p)] = SVNul() + flattn[name(p)] = false + + build-tables(body(m),assign,resets,flattn) + for x in assign do : assign[key(x)] = optimize(value(x)) + for x in resets do : resets[key(x)] = optimize(value(x)) + ;val enables = get-enables(assign,kinds) + ;for x in enables do : enables[key(x)] = optimize(value(x)) + + println-debug("====== Assigns ======") + for x in assign do : println-debug(x) + println-debug("====== Resets ======") + for x in resets do : println-debug(x) + + val table = merge-resets(assign,resets) + println-debug("====== Table ======") + for x in table do : println-debug(x) + val decs = Vector<Stmt>() + val cons = Vector<Stmt>() + expand-whens(ports(m),table,cons) + expand-whens(body(m),table,decs,cons) + InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) defn expand-whens (c:Circuit) -> Circuit : Circuit(info(c),modules*, main(c)) where : @@ -1409,6 +1452,8 @@ public defstruct MaxWidth <: Width : public defstruct ExpWidth <: Width : arg1 : Width +val width-name-hash = HashTable<Symbol,Int>(symbol-hash) + public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T defmethod map (f: Width -> Width, w:Width) -> Width : match(w) : @@ -1600,7 +1645,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod match(map(gen-constraints-s,s)) : (s:DefWire) : DefWire(info(s),name(s),h[name(s)]) (s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s))) - (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType) + (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s)) (s:DefNode) : val l = h[name(s)] val r = gen-constraints(value(s)) @@ -1636,14 +1681,14 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod (e:UIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(firrtl-gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w,width-name-hash)) add(v,WGeq(w*,IntWidth(ceil-log2(value(e))))) UIntValue(value(e),w*) (w) : e (e:SIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(firrtl-gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w,width-name-hash)) add(v,WGeq(w*,IntWidth(1 + ceil-log2(abs(value(e)))))) SIntValue(value(e),w*) (w) : e @@ -1652,7 +1697,9 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod val ports* = for p in ports(m) map : Port(info(p),name(p),direction(p),h[name(p)]) - Module(info(m),name(m),ports*,gen-constraints-s(body(m))) + match(m) : + (m:ExModule) : ExModule(info(m),name(m),ports*) + (m:InModule) : InModule(info(m),name(m),ports*,gen-constraints-s(body(m))) defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTable<Symbol,Type> : defn build-environment (s:Stmt) -> False : @@ -1665,7 +1712,10 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl do(build-environment,s) for p in ports(m) do : h[name(p)] = bundle-field-type(h[name(m)],name(p)) - build-environment(body(m)) + + match(m) : + (m:ExModule) : false + (m:InModule) : build-environment(body(m)) h defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : @@ -1706,15 +1756,18 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : w* val modules* = for m in modules(c) map : - Module{info(m),name(m),_,mapr(reduce-var-widths-w,body(m))} $ - for p in ports(m) map : - Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p))) + val ports* = for p in ports(m) map : + Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p))) + + match(m) : + (m:ExModule) : ExModule(info(m),name(m),ports*) + (m:InModule) : InModule(info(m),name(m),ports*,mapr(reduce-var-widths-w,body(m))) Circuit(info(c),modules*,main(c)) defn remove-unknowns-w (w:Width) -> Width : match(w) : - (w:UnknownWidth) : VarWidth(firrtl-gensym(`w)) + (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash)) (w) : w defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t) @@ -1758,7 +1811,7 @@ public defmethod name (b:Inline) -> String : "Inline Instances" public defmethod short-name (b:Inline) -> String : "inline-instances" defn inline-instances (c:Circuit) : - val h = HashTable<Symbol,Module>(symbol-hash) + val h = HashTable<Symbol,InModule>(symbol-hash) val h-s = HashTable<Symbol,Stmt>(symbol-hash) defn inline-inst (s:Stmt) -> Stmt : match(map(inline-inst,s)) : @@ -1781,30 +1834,32 @@ defn inline-instances (c:Circuit) : (e:WSubfield) : match(kind(exp(e) as WRef)) : (k:InstanceKind) : - WRef(symbol-join([name(exp(e) as WRef) "_" name(e)]),type(e),k,gender(e)) + WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e)) (k:MemKind) : e (e) : e - defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n "_" ref]) + defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n expand-delin ref]) defn rename-e (e:Expression,n:Symbol) -> Expression : match(map(rename-e{_,n},e)) : (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e)) (e:WSubfield) : match(kind(exp(e) as WRef)) : (k:InstanceKind) : - WRef(symbol-join([name(exp(e) as WRef) "_" name(e)]),type(e),k,gender(e)) + WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e)) (k:MemKind) : e (e) : e defn rename-s (s:Stmt,n:Symbol) -> Stmt : map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) : (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s)) (s:DefInstance) : error("Shouldn't be here") - (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s)) (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s)) (s) : s for m in modules(c) do : - h[name(m)] = m - val top = (for m in modules(c) find : name(m) == main(c)) as Module - Circuit(info(c),list(Module(info(top),name(top),ports(top),inline-inst(body(top)))),main(c)) + match(m) : + (m:ExModule) : error("Cannot inline with external modules") + (m:InModule) : h[name(m)] = m + val top = (for m in modules(c) find : name(m) == main(c)) as InModule + Circuit(info(c),list(InModule(info(top),name(top),ports(top),inline-inst(body(top)))),main(c)) ;================= Split Expressions ======================== @@ -1821,34 +1876,38 @@ defn full-name (e:Expression) -> Symbol : (e) : error("Non-supported expression.") defn split-exp (c:Circuit) : - defn split-exp-s (s:Stmt,v:Vector<Stmt>) -> False : + defn split-exp-s (s:Stmt,v:Vector<Stmt>,sh:HashTable<Symbol,Int>) -> False : + defn split-exp-e (e:Expression,n:Symbol|False,info:FileInfo) -> Expression : + match(map(split-exp-e{_,n,info},e)) : + (e:DoPrim) : + val n* = + if n typeof False : firrtl-gensym(`T,sh) + else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh) + add(v,DefNode(info,n*,e)) + WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) + (e) : e match(s) : (s:Begin) : - defn f (s:Stmt) -> False: split-exp-s(s,v) + defn f (s:Stmt) -> False: split-exp-s(s,v,sh) do(f,s) (s:Conditionally) : error("Shouldn't be here") (s:Connect) : match(loc(s)) : - (e:WritePort) : add(v,map(split-exp-e{_,v,full-name(exp(s)),info(s)},s)) - (e) : add(v,map(split-exp-e{_,v,full-name(loc(s)),info(s)},s)) - (s:DefNode) : add(v,map(split-exp-e{_,v,name(s),info(s)},s)) - (s) : add(v,map(split-exp-e{_,v,false,info(s)},s)) + (e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s)) + (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s)) + (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s)) + (s) : add(v,map(split-exp-e{_,false,info(s)},s)) false - defn split-exp-e (e:Expression,v:Vector<Stmt>,n:Symbol|False,info:FileInfo) -> Expression : - match(map(split-exp-e{_,v,n,info},e)): - (e:DoPrim) : - val n* = - if n typeof False : firrtl-gensym(`T) - else : firrtl-gensym(symbol-join([n as Symbol `__])) - add(v,DefNode(info,n*,e)) - WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) - (e) : e Circuit{info(c),_,main(c)} $ for m in modules(c) map : - val v = Vector<Stmt>() - split-exp-s(body(m),v) - Module(info(m),name(m),ports(m),Begin(to-list(v))) + match(m) : + (m:InModule) : + val v = Vector<Stmt>() + val sh = get-sym-hash(m) + split-exp-s(body(m),v,sh) + InModule(info(m),name(m),ports(m),Begin(to-list(v))) + (m:ExModule) : m ;================= Bring to Real IR ======================== ; Returns a new Circuit with only real IR nodes. @@ -1874,5 +1933,60 @@ defn to-real-ir (c:Circuit) : Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : - Module(info(m),name(m), ports(m), to-stmt(body(m))) + match(m) : + (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m))) + (m:ExModule) : m + +;================= Special Rename ======================== +; Returns a new Circuit with only real IR nodes. +public defstruct SpecialRename <: Pass : + original-sym : Symbol + new-sym : Symbol +public defmethod pass (b:SpecialRename) -> (Circuit -> Circuit) : special-rename{original-sym(b),new-sym(b),_:Circuit} +public defmethod name (b:SpecialRename) -> String : "Special Rename" +public defmethod short-name (b:SpecialRename) -> String : "special-rename" + +public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : + defn rename (s:Symbol) -> Symbol : + val y = Vector<String>() + val os = to-string $ original-sym + val ns = to-string $ new-sym + defn rename (st:String) -> False : + if st == os : + add(y,ns) + else if length(st) <= length(os) : + add(y,st) + else : + if substring(st,0,length(os)) == os : + add(y,ns) + rename(substring(st,length(os),length(st))) + else : + add(y,substring(st,0,1)) + rename(substring(st,1,length(st))) + rename(to-string(s)) + to-symbol $ string-join $ to-list(y) + defn to-exp (e:Expression) -> Expression : + match(map(to-exp,e)) : + (e:Ref) : Ref(rename(name(e)), type(e)) + (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e)) + (e) : e + defn to-stmt (s:Stmt) -> Stmt : + match(map(to-exp,s)) : + (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s)) + (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s)) + (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) + (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s)) + (s) : map(to-stmt,s) + + defn to-port (p:Port) -> Port : Port(info(p),rename(name(p)),direction(p),type(p)) + + Circuit(info(c),modules*, main(c)) where : + val modules* = + for m in modules(c) map : + match(m) : + (m:InModule) : InModule(info(m),name(m), map(to-port,ports(m)), to-stmt(body(m))) + (m:ExModule) : m + |