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Diffstat (limited to 'src/main/stanza/passes.stanza')
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index ad165353..324630f0 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -869,7 +869,7 @@ defn lower-module (m:Module,table:HashTable<Symbol,List<KeyValue<Expression,Flip (s:DefWire) : table[name(s)] = get-entries(name(s),type(s)) (s:DefRegister) : table[name(s)] = get-entries(name(s),type(s)) - table[to-symbol("~.init" % to-string(name(s)))] = get-entries(to-symbol("~#init" % to-string(name(s))),type(s)) ; TODO, we are keeping WRegInits around + table[to-symbol("~.init" % [to-string(name(s))])] = get-entries(to-symbol("~#init" % [to-string(name(s))]),type(s)) ; TODO, we are keeping WRegInits around (s:DefInstance) : val r = WRef(name(s),type(module(s)),InstanceKind(),FEMALE) val ports = table[name(module(s) as WRef)] |