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Diffstat (limited to 'src/main/stanza/firrtl-test-main.stanza')
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 177 |
1 files changed, 0 insertions, 177 deletions
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza deleted file mode 100644 index 4fcc9dee..00000000 --- a/src/main/stanza/firrtl-test-main.stanza +++ /dev/null @@ -1,177 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -#include<"core/stringeater.stanza"> -#include<"core/macro-utils.stanza"> -#include<"compiler/stz-algorithms.stanza"> -#include<"compiler/stz-parser.stanza"> -#include<"compiler/stz-lexer.stanza"> -#include("bigint2.stanza") -#include("firrtl-lexer.stanza") -#include("firrtl-ir.stanza") -#include("ir-utils.stanza") -#include("ir-parser.stanza") -#include("passes.stanza") -#include("chirrtl.stanza") -#include("primop.stanza") -#include("errors.stanza") -#include("compilers.stanza") -#include("firrtl.stanza") -;#include("flo.stanza") -;#include("verilog.stanza") -;#include("symbolic-value.stanza") - -;Custom Packages -;#include("custom-passes.stanza") -;#include("custom-compiler.stanza") - -defpackage firrtl-main : - import core - import verse - import firrtl/parser - import firrtl/passes - import firrtl/ir2 - import firrtl/lexer - import stz/parser - import firrtl/ir-utils - import firrtl/compiler - import firrtl/chirrtl - import firrtl/firrtl - ;Custom Packages - ;import firrtl/custom-passes - ;import firrtl/custom-compiler - -defn set-printvars! (p:List<Char>) : - if contains(p,'t') : PRINT-TYPES = true - if contains(p,'k') : PRINT-KINDS = true - if contains(p,'w') : PRINT-WIDTHS = true - if contains(p,'T') : PRINT-TWIDTHS = true - if contains(p,'g') : PRINT-GENDERS = true - if contains(p,'c') : PRINT-CIRCUITS = true - if contains(p,'d') : PRINT-DEBUG = true - if contains(p,'i') : PRINT-INFO = true - -defn get-passes (pass-names:List<String>) -> List<Pass> : - for n in pass-names map : - val p = for p in append(standard-passes,chirrtl-passes) find : - n == short-name(p) - if p == false : - error(to-string $ ["Unrecognized pass flag: " n]) - p as Pass - -defn main () : - val args = commandline-arguments() - var input = false - var output = false - var firms = Vector<String>() - var compiler = false - val pass-names = Vector<String>() - val pass-args = Vector<String>() - var printvars = "" - var last-s = "" - var backend = false - - val prev-out = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-ERROR - - - for (s in args, i in 0 to false) do : - if s == "-i" : last-s = s - else if s == "-o" : last-s = s - else if s == "-x" : last-s = s - else if s == "-X" : last-s = s - else if s == "-p" : last-s = s - else if s == "-s" : last-s = s - else if s == "-m" : last-s = s - else if s == "-b" : last-s = s - else : - if last-s == "-i" : input = args[i] - if last-s == "-o" : output = args[i] - if last-s == "-x" : add(pass-names,args[i]) - if last-s == "-X" : compiler = args[i] - if last-s == "-p" : printvars = to-string([printvars args[i]]) - if last-s == "-s" : add(pass-args,args[i]) - if last-s == "-m" : add(firms,args[i]) - if last-s == "-b" : backend = args[i] - - var with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-OUTPUT - f() - CURRENT-OUTPUT-STREAM = prev-stream - - if input == false : - error("No input file provided. Use -i flag.") - if output != false and output != "-": - with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - val out-stream = FileOutputStream(output as String) - CURRENT-OUTPUT-STREAM = out-stream - f() - CURRENT-OUTPUT-STREAM = prev-stream - close(out-stream) - - if compiler == false and backend == false and length(pass-names) == 0 : - error("Must specify a compiler or a backend. Use -X flag or -b flag.") - - val lexed = lex-file(input as String) - val circuit = parse-firrtl(lexed) - - val modules* = Vector<Module>() - for m in modules(circuit) do : - add(modules*,m) - - val included-c = - for m in firms map : - val lexed = lex-file(m as String) - parse-firrtl(lexed) - - for c in included-c do : - for m in modules(c) do : - add(modules*,m) - - val circuit* = Circuit(info(circuit),to-list(modules*),main(circuit)) - - set-printvars!(to-list(printvars)) - - if compiler == false : - var c*:Circuit = run-passes(circuit*,get-passes(to-list(pass-names))) - switch {_ == backend} : - "verilog" : run-backend(c*,LoToVerilog(with-output)) - "firrtl" : run-backend(c*,FIRRTL(with-output)) - else : error("Invalid backend flag!") - else : - switch {_ == compiler} : - ;"flo" : error("Flo backend not currently supported.") - ; run-passes(circuit*,StandardFlo(with-output)) - "verilog" : run-passes(circuit*,StandardVerilog(with-output)) - "firrtl" : run-passes(circuit*,StandardFIRRTL(with-output)) - "lofirrtl" : run-passes(circuit*,StandardLoFIRRTL(with-output)) - ;"verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args)) - else : error("Invalid compiler flag") - - CURRENT-OUTPUT-STREAM = prev-out -main() |