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diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
deleted file mode 100644
index 95686189..00000000
--- a/src/main/stanza/custom-compiler.stanza
+++ /dev/null
@@ -1,71 +0,0 @@
-;Copyright (c) 2014 - 2016 The Regents of the University of
-;California (Regents). All Rights Reserved.  Redistribution and use in
-;source and binary forms, with or without modification, are permitted
-;provided that the following conditions are met:
-;   * Redistributions of source code must retain the above
-;     copyright notice, this list of conditions and the following
-;     two paragraphs of disclaimer.
-;   * Redistributions in binary form must reproduce the above
-;     copyright notice, this list of conditions and the following
-;     two paragraphs of disclaimer in the documentation and/or other materials
-;     provided with the distribution.
-;   * Neither the name of the Regents nor the names of its contributors
-;     may be used to endorse or promote products derived from this
-;     software without specific prior written permission.
-;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
-;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
-;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
-;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
-;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
-;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
-;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
-;MODIFICATIONS.
-;defpackage firrtl/custom-compiler :
-;   import core
-;   import verse
-;   import firrtl/ir-utils
-;   import firrtl/ir2
-;   import firrtl/passes
-;   import firrtl/errors
-;   import firrtl/verilog
-;   import firrtl/custom-passes
-;
-;public defstruct InstrumentedVerilog <: Compiler :
-;   with-output: (() -> False) -> False   with: (as-method => true)
-;   args: List<String>
-;public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
-;   to-list $ [
-;      WhenCoverage(args(c)[0],args(c)[1])
-;      RemoveSpecialChars()
-;      RemoveScopes()
-;      CheckHighForm()
-;      TempElimination()
-;      ToWorkingIR()
-;      ;; MakeExplicitReset()
-;      ResolveKinds()
-;      CheckKinds()
-;      InferTypes()
-;      CheckTypes()
-;      ResolveGenders()
-;      CheckGenders()
-;      ExpandAccessors()
-;      LowerToGround()
-;      InlineIndexed()
-;      InferTypes()
-;      CheckGenders()
-;      ExpandWhens()
-;      InferWidths()
-;      ;Pad()
-;      ConstProp()
-;      SplitExp()
-;      ToRealIR()
-;      ;RemoveSpecialChars()
-;      CheckHighForm()
-;      CheckLowForm()
-;      CheckInitialization()
-;      Verilog(with-output(c))
-;   ]
-;
-;