diff options
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 762ed9a8..efa8c992 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -12,7 +12,7 @@ public defstruct StandardFlo <: Compiler : file: String with: (as-method => true) public defmethod passes (c:StandardFlo) -> List<Pass> : to-list $ [ - CheckHighForm() + CheckHighForm(expand-delin) TempElimination() ToWorkingIR() MakeExplicitReset() @@ -31,6 +31,9 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : Inline() SplitExp() ToRealIR() + SpecialRename(`#,`_) + SpecialRename(`$,`::) + CheckHighForm(`::) Flo(file(c)) ] @@ -38,7 +41,7 @@ public defstruct StandardVerilog <: Compiler : file: String with: (as-method => true) public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ - CheckHighForm() + CheckHighForm(expand-delin) TempElimination() ToWorkingIR() MakeExplicitReset() @@ -53,9 +56,9 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ExpandIndexedConnects() ExpandWhens() InferWidths() - ;Inline() SplitExp() ToRealIR() + SpecialRename(`#,`_) Verilog(file(c)) ] |