diff options
Diffstat (limited to 'src/main/scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/DeadCodeElimination.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 5199276c..bf7ff7eb 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -151,6 +151,9 @@ class DeadCodeElimination extends Transform { case ext: ExtModule => // Connect all inputs to all outputs val node = LogicNode(ext) + // Don't touch external modules *unless* they are specifically marked as doTouch + // Simply marking the extmodule itself is sufficient to prevent inputs from being removed + if (!doTouchExtMods.contains(ext.name)) depGraph.addEdge(circuitSink, node) ext.ports.foreach { case Port(_, pname, _, AnalogType(_)) => depGraph.addEdge(LogicNode(ext.name, pname), node) @@ -158,7 +161,7 @@ class DeadCodeElimination extends Transform { case Port(_, pname, Output, _) => val portNode = LogicNode(ext.name, pname) depGraph.addEdge(portNode, node) - // Don't touch external modules *unless* they are specifically marked as doTouch + // Also mark all outputs as circuit sinks (unless marked doTouch obviously) if (!doTouchExtMods.contains(ext.name)) depGraph.addEdge(circuitSink, portNode) case Port(_, pname, Input, _) => depGraph.addEdge(node, LogicNode(ext.name, pname)) } |