diff options
Diffstat (limited to 'src/main/scala/midas/Utils.scala')
| -rw-r--r-- | src/main/scala/midas/Utils.scala | 69 |
1 files changed, 42 insertions, 27 deletions
diff --git a/src/main/scala/midas/Utils.scala b/src/main/scala/midas/Utils.scala index d2c61c1b..b9006b59 100644 --- a/src/main/scala/midas/Utils.scala +++ b/src/main/scala/midas/Utils.scala @@ -6,6 +6,20 @@ import firrtl.Utils._ object Utils { + // Merges a sequence of maps via the provided function f + // Taken from: https://groups.google.com/forum/#!topic/scala-user/HaQ4fVRjlnU + def merge[K, V](maps: Seq[Map[K, V]])(f: (K, V, V) => V): Map[K, V] = { + maps.foldLeft(Map.empty[K, V]) { case (merged, m) => + m.foldLeft(merged) { case (acc, (k, v)) => + acc.get(k) match { + case Some(existing) => acc.updated(k, f(k, existing, v)) + case None => acc.updated(k, v) + } + } + } + } + + // Takes a set of strings or ints and returns equivalent expression node // Strings correspond to subfields/references, ints correspond to indexes // eg. Seq(io, port, ready) => io.port.ready @@ -23,7 +37,7 @@ object Utils { else Index(rec(names.tail), head, UnknownType) // String -> Ref/Subfield case head: String => - if( names.tail.isEmpty ) Ref("head", UnknownType) + if( names.tail.isEmpty ) Ref(head, UnknownType) else Subfield(rec(names.tail), head, UnknownType) case _ => throw new Exception("Invalid argument type to buildExp! " + names) } @@ -85,41 +99,42 @@ object Utils { def buildSimQueue(name: String, tpe: Type): Module = { val templatedQueue = """ + circuit `NAME: module `NAME : - input clock : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : `TYPE}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : `TYPE}, count : UInt<3>} + input hostClock : Clock + input hostReset : UInt<1> + output io : {flip enq : {flip hostReady : UInt<1>, hostValid : UInt<1>, hostBits : `TYPE}, deq : {flip hostReady : UInt<1>, hostValid : UInt<1>, hostBits : `TYPE}, count : UInt<3>} io.count := UInt<1>("h00") - io.deq.bits.surprise.no := UInt<1>("h00") - io.deq.bits.surprise.yes := UInt<1>("h00") - io.deq.bits.store := UInt<1>("h00") - io.deq.bits.data := UInt<1>("h00") - io.deq.bits.addr := UInt<1>("h00") - io.deq.valid := UInt<1>("h00") - io.enq.ready := UInt<1>("h00") - cmem ram : `TYPE[4], clock - reg T_80 : UInt<2>, clock, reset + //io.deq.hostBits.surprise.no := UInt<1>("h00") + //io.deq.hostBits.surprise.yes := UInt<1>("h00") + //io.deq.hostBits.store := UInt<1>("h00") + //io.deq.hostBits.data := UInt<1>("h00") + //io.deq.hostBits.addr := UInt<1>("h00") + io.deq.hostValid := UInt<1>("h00") + io.enq.hostReady := UInt<1>("h00") + cmem ram : `TYPE[4], hostClock + reg T_80 : UInt<2>, hostClock, hostReset onreset T_80 := UInt<2>("h00") - reg T_82 : UInt<2>, clock, reset + reg T_82 : UInt<2>, hostClock, hostReset onreset T_82 := UInt<2>("h00") - reg maybe_full : UInt<1>, clock, reset + reg maybe_full : UInt<1>, hostClock, hostReset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_80, T_82) node T_87 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_87) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_93 = and(io.enq.ready, io.enq.valid) + node do_flow = and(maybe_flow, io.deq.hostReady) + node T_93 = and(io.enq.hostReady, io.enq.hostValid) node T_95 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_93, T_95) - node T_97 = and(io.deq.ready, io.deq.valid) + node T_97 = and(io.deq.hostReady, io.deq.hostValid) node T_99 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_97, T_99) when do_enq : infer accessor T_101 = ram[T_80] - T_101 <> io.enq.bits + T_101 <> io.enq.hostBits node T_109 = eq(T_80, UInt<2>("h03")) node T_111 = and(UInt<1>("h00"), T_109) node T_114 = addw(T_80, UInt<1>("h01")) @@ -138,20 +153,20 @@ object Utils { maybe_full := do_enq skip node T_126 = eq(empty, UInt<1>("h00")) - node T_128 = and(UInt<1>("h00"), io.enq.valid) + node T_128 = and(UInt<1>("h00"), io.enq.hostValid) node T_129 = or(T_126, T_128) - io.deq.valid := T_129 + io.deq.hostValid := T_129 node T_131 = eq(full, UInt<1>("h00")) - node T_133 = and(UInt<1>("h00"), io.deq.ready) + node T_133 = and(UInt<1>("h00"), io.deq.hostReady) node T_134 = or(T_131, T_133) - io.enq.ready := T_134 + io.enq.hostReady := T_134 infer accessor T_135 = ram[T_82] wire T_149 : `TYPE T_149 <> T_135 when maybe_flow : - T_149 <> io.enq.bits + T_149 <> io.enq.hostBits skip - io.deq.bits <> T_149 + io.deq.hostBits <> T_149 node ptr_diff = subw(T_80, T_82) node T_157 = and(maybe_full, ptr_match) node T_158 = cat(T_157, ptr_diff) @@ -162,8 +177,8 @@ object Utils { replaceAllLiterally("`TYPE", tpe.serialize) // Generate initial values //val bitsField = Field("bits", Default, tpe) - println(concreteQueue.stripMargin) - firrtl.Parser.parseModule(concreteQueue) + val ast = firrtl.Parser.parse(concreteQueue.split("\n")) + ast.modules.head } } |