diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms')
| -rw-r--r-- | src/main/scala/firrtl/transforms/DeadCodeElimination.scala | 7 | ||||
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveWires.scala | 20 |
2 files changed, 21 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 1d9bfd0e..f72585d1 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -11,6 +11,7 @@ import firrtl.analyses.InstanceKeyGraph import firrtl.Mappers._ import firrtl.Utils.{kind, throwInternalError} import firrtl.MemoizedHash._ +import firrtl.backends.experimental.smt.random.DefRandom import firrtl.options.{Dependency, RegisteredTransform, ShellOption} import collection.mutable @@ -126,6 +127,11 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend val node = LogicNode(mod.name, name) depGraph.addVertex(node) Seq(clock, reset, init).flatMap(getDeps(_)).foreach(ref => depGraph.addPairWithEdge(node, ref)) + case DefRandom(_, name, _, clock, en) => + val node = LogicNode(mod.name, name) + depGraph.addVertex(node) + val inputs = clock ++: en +: Nil + inputs.flatMap(getDeps).foreach(ref => depGraph.addPairWithEdge(node, ref)) case DefNode(_, name, value) => val node = LogicNode(mod.name, name) depGraph.addVertex(node) @@ -225,6 +231,7 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend val tpe = decl match { case _: DefNode => "node" case _: DefRegister => "reg" + case _: DefRandom => "rand" case _: DefWire => "wire" case _: Port => "port" case _: DefMemory => "mem" diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index f2907db2..7500b386 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -11,6 +11,7 @@ import firrtl.WrappedExpression._ import firrtl.graph.{CyclicException, MutableDiGraph} import firrtl.options.Dependency import firrtl.Utils.getGroundZero +import firrtl.backends.experimental.smt.random.DefRandom import scala.collection.mutable import scala.util.{Failure, Success, Try} @@ -41,13 +42,13 @@ class RemoveWires extends Transform with DependencyAPIMigration { case _ => false } - // Extract all expressions that are references to a Node, Wire, or Reg + // Extract all expressions that are references to a Node, Wire, Reg or Rand // Since we are operating on LowForm, they can only be WRefs private def extractNodeWireRegRefs(expr: Expression): Seq[WRef] = { val refs = mutable.ArrayBuffer.empty[WRef] def rec(e: Expression): Expression = { e match { - case ref @ WRef(_, _, WireKind | NodeKind | RegKind, _) => refs += ref + case ref @ WRef(_, _, WireKind | NodeKind | RegKind | RandomKind, _) => refs += ref case nested @ (_: Mux | _: DoPrim | _: ValidIf) => nested.foreach(rec) case _ => // Do nothing } @@ -59,8 +60,9 @@ class RemoveWires extends Transform with DependencyAPIMigration { // Transform netlist into DefNodes private def getOrderedNodes( - netlist: mutable.LinkedHashMap[WrappedExpression, (Seq[Expression], Info)], - regInfo: mutable.Map[WrappedExpression, DefRegister] + netlist: mutable.LinkedHashMap[WrappedExpression, (Seq[Expression], Info)], + regInfo: mutable.Map[WrappedExpression, DefRegister], + randInfo: mutable.Map[WrappedExpression, DefRandom] ): Try[Seq[Statement]] = { val digraph = new MutableDiGraph[WrappedExpression] for ((sink, (exprs, _)) <- netlist) { @@ -80,7 +82,8 @@ class RemoveWires extends Transform with DependencyAPIMigration { ordered.map { key => val WRef(name, _, kind, _) = key.e1 kind match { - case RegKind => regInfo(key) + case RegKind => regInfo(key) + case RandomKind => randInfo(key) case WireKind | NodeKind => val (Seq(rhs), info) = netlist(key) DefNode(info, name, rhs) @@ -100,6 +103,8 @@ class RemoveWires extends Transform with DependencyAPIMigration { val wireInfo = mutable.HashMap.empty[WrappedExpression, Info] // Additional info about registers val regInfo = mutable.HashMap.empty[WrappedExpression, DefRegister] + // Additional info about rand statements + val randInfo = mutable.HashMap.empty[WrappedExpression, DefRandom] def onStmt(stmt: Statement): Statement = { stmt match { @@ -115,6 +120,9 @@ class RemoveWires extends Transform with DependencyAPIMigration { val initDep = Some(reg.init).filter(we(WRef(reg)) != we(_)) // Dependency exists IF reg doesn't init itself regInfo(we(WRef(reg))) = reg netlist(we(WRef(reg))) = (Seq(reg.clock) ++ resetDep ++ initDep, reg.info) + case rand: DefRandom => + randInfo(we(Reference(rand))) = rand + netlist(we(Reference(rand))) = (rand.clock ++: rand.en +: List(), rand.info) case decl: CanBeReferenced => // Keep all declarations except for nodes and non-Analog wires and "other" statements. // Thus this is expected to match DefInstance and DefMemory which both do not connect to @@ -148,7 +156,7 @@ class RemoveWires extends Transform with DependencyAPIMigration { m match { case mod @ Module(info, name, ports, body) => onStmt(body) - getOrderedNodes(netlist, regInfo) match { + getOrderedNodes(netlist, regInfo, randInfo) match { case Success(logic) => Module(info, name, ports, Block(List() ++ decls ++ logic ++ otherStmts)) // If we hit a CyclicException, just abort removing wires |