diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms')
23 files changed, 128 insertions, 151 deletions
diff --git a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala index 07cf09b0..f922a038 100644 --- a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala +++ b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala @@ -55,17 +55,15 @@ class BlackBoxNotFoundException(fileName: String, message: String) extends Firrt * will set the directory where the Verilog will be written. This annotation is typically be * set by the execution harness, or directly in the tests */ -class BlackBoxSourceHelper extends firrtl.Transform with PreservesAll[Transform] { +class BlackBoxSourceHelper extends Transform with DependencyAPIMigration with PreservesAll[Transform] { import BlackBoxSourceHelper._ private val DefaultTargetDir = new File(".") - override def inputForm: CircuitForm = LowForm - override def outputForm: CircuitForm = LowForm - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty /** Collect BlackBoxHelperAnnos and and find the target dir if specified * @param annos a list of generic annotations for this transform diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala index 53be9a98..2660c848 100644 --- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala +++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala @@ -94,18 +94,19 @@ case class CombinationalPath(sink: ReferenceTarget, sources: Seq[ReferenceTarget * @note The pass relies on ExtModulePathAnnotations to find loops through ExtModules * @note The pass will throw exceptions on "false paths" */ -class CheckCombLoops extends Transform with RegisteredTransform with PreservesAll[Transform] { - def inputForm = LowForm - def outputForm = LowForm +class CheckCombLoops extends Transform + with RegisteredTransform + with DependencyAPIMigration + with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.MidForm ++ + override def prerequisites = firrtl.stage.Forms.MidForm ++ Seq( Dependency(passes.LowerTypes), Dependency(passes.Legalize), Dependency(firrtl.transforms.RemoveReset) ) - override val optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty - override val dependents = Seq.empty + override def dependents = Seq.empty import CheckCombLoops._ diff --git a/src/main/scala/firrtl/transforms/CombineCats.scala b/src/main/scala/firrtl/transforms/CombineCats.scala index 8f5972e1..4f678826 100644 --- a/src/main/scala/firrtl/transforms/CombineCats.scala +++ b/src/main/scala/firrtl/transforms/CombineCats.scala @@ -53,19 +53,17 @@ object CombineCats { * Use [[MaxCatLenAnnotation]] to limit the number of elements that can be concatenated. * The default maximum number of elements is 10. */ -class CombineCats extends Transform with PreservesAll[Transform] { - def inputForm: LowForm.type = LowForm - def outputForm: LowForm.type = LowForm +class CombineCats extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowForm ++ + override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(passes.RemoveValidIf), Dependency[firrtl.transforms.ConstantPropagation], Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency(firrtl.passes.SplitExpressions) ) - override val optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty - override val dependents = Seq( + override def dependents = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala index 18577147..b97ce94b 100644 --- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala +++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala @@ -98,20 +98,18 @@ object ConstantPropagation { } -class ConstantPropagation extends Transform with ResolvedAnnotationPaths { +class ConstantPropagation extends Transform with DependencyAPIMigration with ResolvedAnnotationPaths { import ConstantPropagation._ - def inputForm = LowForm - def outputForm = LowForm - override val prerequisites = + override def prerequisites = ((new mutable.LinkedHashSet()) ++ firrtl.stage.Forms.LowForm - Dependency(firrtl.passes.Legalize) + Dependency(firrtl.passes.RemoveValidIf)).toSeq - override val optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty - override val dependents = + override def dependents = Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency(firrtl.passes.SplitExpressions), Dependency[SystemVerilogEmitter], diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 04f1c7d2..0262f535 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -29,12 +29,13 @@ import collection.mutable * circumstances of their instantiation in their parent module, they will still not be removed. To * remove such modules, use the [[NoDedupAnnotation]] to prevent deduplication. */ -class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with RegisteredTransform +class DeadCodeElimination extends Transform + with ResolvedAnnotationPaths + with RegisteredTransform + with DependencyAPIMigration with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm - override val prerequisites = firrtl.stage.Forms.LowForm ++ + override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency[firrtl.transforms.ConstantPropagation], Dependency(firrtl.passes.memlib.VerilogMemDelays), @@ -42,9 +43,9 @@ class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with Re Dependency[firrtl.transforms.CombineCats], Dependency(passes.CommonSubexpressionElimination) ) - override val optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty - override val dependents = + override def dependents = Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], Dependency[firrtl.transforms.FlattenRegUpdate], diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 5caa9228..62f9c3f5 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -39,13 +39,11 @@ case object NoCircuitDedupAnnotation extends NoTargetAnnotation with HasShellOpt * Specifically, the restriction of instance loops must have been checked, or else this pass can * infinitely recurse */ -class DedupModules extends Transform with PreservesAll[Transform] { - def inputForm: CircuitForm = HighForm - def outputForm: CircuitForm = HighForm +class DedupModules extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.Resolved + override def prerequisites = firrtl.stage.Forms.Resolved - override val dependents = Seq.empty + override def dependents = Seq.empty /** Deduplicate a Circuit * @param state Input Firrtl AST diff --git a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala index 59d14ab2..6a7e75e0 100644 --- a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala +++ b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala @@ -2,7 +2,7 @@ package firrtl.transforms -import firrtl.{CircuitState, Namespace, PrimOps, Transform, UnknownForm, Utils, WRef} +import firrtl.{CircuitState, DependencyAPIMigration, Namespace, PrimOps, Transform, Utils, WRef} import firrtl.ir._ import firrtl.Mappers._ import firrtl.options.{Dependency, PreservesAll} @@ -107,15 +107,13 @@ object FixAddingNegativeLiterals { * the literal and thus not all expressions in the add are the same. This is fixed here when we directly * subtract the literal instead. */ -class FixAddingNegativeLiterals extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class FixAddingNegativeLiterals extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = Forms.LowFormMinimumOptimized :+ Dependency[BlackBoxSourceHelper] + override def prerequisites = Forms.LowFormMinimumOptimized :+ Dependency[BlackBoxSourceHelper] - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(FixAddingNegativeLiterals.fixupModule) diff --git a/src/main/scala/firrtl/transforms/Flatten.scala b/src/main/scala/firrtl/transforms/Flatten.scala index 68cfa3d0..8826a370 100644 --- a/src/main/scala/firrtl/transforms/Flatten.scala +++ b/src/main/scala/firrtl/transforms/Flatten.scala @@ -7,7 +7,9 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.annotations._ import scala.collection.mutable +import firrtl.options.PreservesAll import firrtl.passes.{InlineInstances,PassException} +import firrtl.stage.Forms /** Tags an annotation to be consumed by this transform */ case class FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named] { @@ -22,9 +24,11 @@ case class FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named * @note Flattening a module means inlining all its fully-defined child instances * @note Instances of extmodules are not (and cannot be) inlined */ -class Flatten extends Transform { - def inputForm = LowForm - def outputForm = LowForm +class Flatten extends Transform with DependencyAPIMigration with PreservesAll[Transform] { + + override def prerequisites = Forms.LowForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.LowEmitters val inlineTransform = new InlineInstances diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala index eadbb0cb..242f238e 100644 --- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala +++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala @@ -105,11 +105,9 @@ object FlattenRegUpdate { * the register */ // TODO Preserve source locators -class FlattenRegUpdate extends Transform { - def inputForm = UnknownForm - def outputForm = UnknownForm +class FlattenRegUpdate extends Transform with DependencyAPIMigration { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], @@ -117,9 +115,9 @@ class FlattenRegUpdate extends Transform { Dependency[InlineCastsTransform], Dependency[LegalizeClocksTransform] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty override def invalidates(a: Transform): Boolean = a match { case _: DeadCodeElimination => true diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 9e3d639d..083ddbb7 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -6,6 +6,7 @@ import firrtl.ir._ import firrtl.annotations.{Annotation, ComponentName} import firrtl.passes.{InferTypes, LowerTypes, ResolveKinds} import firrtl.graph.MutableDiGraph +import firrtl.stage.Forms import scala.collection.mutable @@ -44,11 +45,17 @@ case class GroupAnnotation(components: Seq[ComponentName], newModule: String, ne /** * Splits a module into multiple modules by grouping its components via [[GroupAnnotation]]'s */ -class GroupComponents extends firrtl.Transform { +class GroupComponents extends Transform with DependencyAPIMigration { type MSet[T] = mutable.Set[T] - def inputForm: CircuitForm = MidForm - def outputForm: CircuitForm = MidForm + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters + + override def invalidates(a: Transform): Boolean = a match { + case InferTypes | ResolveKinds => true + case _ => false + } override def execute(state: CircuitState): CircuitState = { val groups = state.annotations.collect {case g: GroupAnnotation => g} @@ -60,10 +67,7 @@ class GroupComponents extends firrtl.Transform { groupModule(m, module2group(m.name).filter(_.components.nonEmpty), mnamespace) case other => Seq(other) } - val cs = state.copy(circuit = state.circuit.copy(modules = newModules)) - /* @todo move ResolveKinds and InferTypes out */ - val csx = ResolveKinds.execute(InferTypes.execute(cs)) - csx + state.copy(circuit = state.circuit.copy(modules = newModules)) } def groupModule(m: Module, groups: Seq[GroupAnnotation], mnamespace: Namespace): Seq[Module] = { @@ -350,13 +354,11 @@ class GroupComponents extends firrtl.Transform { * Splits a module into multiple modules by grouping its components via [[GroupAnnotation]]'s * Tries to deduplicate the resulting circuit */ -class GroupAndDedup extends Transform { - def inputForm: CircuitForm = MidForm - def outputForm: CircuitForm = MidForm +class GroupAndDedup extends GroupComponents { - override def execute(state: CircuitState): CircuitState = { - val cs = new GroupComponents().execute(state) - val csx = new DedupModules().execute(cs) - csx + override def invalidates(a: Transform): Boolean = a match { + case _: DedupModules => true + case _ => super.invalidates(a) } + } diff --git a/src/main/scala/firrtl/transforms/IdentityTransform.scala b/src/main/scala/firrtl/transforms/IdentityTransform.scala index a39ca4b7..4faa5cd0 100644 --- a/src/main/scala/firrtl/transforms/IdentityTransform.scala +++ b/src/main/scala/firrtl/transforms/IdentityTransform.scala @@ -7,9 +7,14 @@ import firrtl.{CircuitForm, CircuitState, Transform} /** Transform that applies an identity function. This returns an unmodified [[CircuitState]]. * @param form the input and output [[CircuitForm]] */ +@deprecated( + "mix-in firrtl.options.IdentityLike[CircuitState]. IdentityTransform will be removed in 1.4.", + "FIRRTL 1.3" +) class IdentityTransform(form: CircuitForm) extends Transform { final override def inputForm: CircuitForm = form + final override def outputForm: CircuitForm = form final def execute(state: CircuitState): CircuitState = state diff --git a/src/main/scala/firrtl/transforms/InferResets.scala b/src/main/scala/firrtl/transforms/InferResets.scala index 4342f276..1798e3d8 100644 --- a/src/main/scala/firrtl/transforms/InferResets.scala +++ b/src/main/scala/firrtl/transforms/InferResets.scala @@ -110,12 +110,9 @@ object InferResets { * generator languages like Chisel can infer differently */ // TODO should we error if a DefMemory is of type AsyncReset? In CheckTypes? -class InferResets extends Transform { +class InferResets extends Transform with DependencyAPIMigration { - def inputForm: CircuitForm = UnknownForm - def outputForm: CircuitForm = UnknownForm - - override val prerequisites = + override def prerequisites = Seq( Dependency(passes.ResolveKinds), Dependency(passes.InferTypes), Dependency(passes.Uniquify), diff --git a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala index 9ed5aafa..1c49a9b2 100644 --- a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala +++ b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala @@ -94,18 +94,16 @@ object InlineBitExtractionsTransform { } /** Inline nodes that are simple bits */ -class InlineBitExtractionsTransform extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class InlineBitExtractionsTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(InlineBitExtractionsTransform.onMod(_)) diff --git a/src/main/scala/firrtl/transforms/InlineCasts.scala b/src/main/scala/firrtl/transforms/InlineCasts.scala index e6800d60..5789a87c 100644 --- a/src/main/scala/firrtl/transforms/InlineCasts.scala +++ b/src/main/scala/firrtl/transforms/InlineCasts.scala @@ -66,20 +66,18 @@ object InlineCastsTransform { } /** Inline nodes that are simple casts */ -class InlineCastsTransform extends Transform { - def inputForm = UnknownForm - def outputForm = UnknownForm +class InlineCastsTransform extends Transform with DependencyAPIMigration { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], Dependency[InlineBitExtractionsTransform], Dependency[PropagatePresetAnnotations] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty override def invalidates(a: Transform): Boolean = a match { case _: LegalizeClocksTransform => true diff --git a/src/main/scala/firrtl/transforms/LegalizeClocks.scala b/src/main/scala/firrtl/transforms/LegalizeClocks.scala index d87cd735..2e3cb8ff 100644 --- a/src/main/scala/firrtl/transforms/LegalizeClocks.scala +++ b/src/main/scala/firrtl/transforms/LegalizeClocks.scala @@ -59,20 +59,18 @@ object LegalizeClocksTransform { } /** Ensure Clocks to be emitted are legal Verilog */ -class LegalizeClocksTransform extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class LegalizeClocksTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], Dependency[InlineBitExtractionsTransform], Dependency[InlineCastsTransform] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(LegalizeClocksTransform.onMod(_)) diff --git a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala index f36ee5e0..f9c55270 100644 --- a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala +++ b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala @@ -36,18 +36,16 @@ object PropagatePresetAnnotations { * * @note This pass must run before InlineCastsTransform */ -class PropagatePresetAnnotations extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class PropagatePresetAnnotations extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic]) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty import PropagatePresetAnnotations._ diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala index fdb0090e..214692e6 100644 --- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala +++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala @@ -20,9 +20,7 @@ import scala.collection.mutable * @define implicitNamespace @param ns an encolosing [[Namespace]] with which new names must not conflict * @define implicitScope @param scope the enclosing scope of this name. If [[None]], then this is a [[Circuit]] name */ -class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { - val inputForm: CircuitForm = UnknownForm - val outputForm: CircuitForm = UnknownForm +class RemoveKeywordCollisions(keywords: Set[String]) extends Transform with DependencyAPIMigration { private type ModuleType = mutable.HashMap[String, ir.Type] private val inlineDelim = "_" @@ -235,7 +233,7 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { /** Transform that removes collisions with Verilog keywords */ class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], @@ -245,8 +243,8 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAl Dependency[FlattenRegUpdate], Dependency(passes.VerilogModulusCleanup) ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty } diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index 75d64b76..128496d4 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -15,17 +15,15 @@ import scala.collection.{immutable, mutable} * * @note This pass must run after LowerTypes */ -object RemoveReset extends Transform { - def inputForm = LowForm - def outputForm = LowForm +object RemoveReset extends Transform with DependencyAPIMigration { - override val prerequisites = firrtl.stage.Forms.MidForm ++ + override def prerequisites = firrtl.stage.Forms.MidForm ++ Seq( Dependency(passes.LowerTypes), Dependency(passes.Legalize) ) - override val optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty - override val dependents = Seq.empty + override def dependents = Seq.empty override def invalidates(a: Transform): Boolean = a match { case firrtl.passes.ResolveFlows => true diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index 5e6b7910..444df4b1 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -20,19 +20,17 @@ import scala.util.{Try, Success, Failure} * wires have multiple connections that may be impossible to order in a * flow-foward way */ -class RemoveWires extends Transform with PreservesAll[Transform] { - def inputForm = LowForm - def outputForm = LowForm +class RemoveWires extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.MidForm ++ + override def prerequisites = firrtl.stage.Forms.MidForm ++ Seq( Dependency(passes.LowerTypes), Dependency(passes.Legalize), Dependency(transforms.RemoveReset), Dependency[transforms.CheckCombLoops] ) - override val optionalPrerequisites = Seq(Dependency[checks.CheckResets]) + override def optionalPrerequisites = Seq(Dependency[checks.CheckResets]) - override val dependents = Seq.empty + override def dependents = Seq.empty // Extract all expressions that are references to a Node, Wire, or Reg // Since we are operating on LowForm, they can only be WRefs diff --git a/src/main/scala/firrtl/transforms/RenameModules.scala b/src/main/scala/firrtl/transforms/RenameModules.scala index af17dda9..c8a757ba 100644 --- a/src/main/scala/firrtl/transforms/RenameModules.scala +++ b/src/main/scala/firrtl/transforms/RenameModules.scala @@ -5,6 +5,8 @@ package firrtl.transforms import firrtl.analyses.{InstanceGraph, ModuleNamespaceAnnotation} import firrtl.ir._ import firrtl._ +import firrtl.options.PreservesAll +import firrtl.stage.Forms import scala.collection.mutable @@ -12,9 +14,11 @@ import scala.collection.mutable * * using namespace created by [[analyses.GetNamespace]], create unique names for modules */ -class RenameModules extends Transform { - def inputForm: LowForm.type = LowForm - def outputForm: LowForm.type = LowForm +class RenameModules extends Transform with DependencyAPIMigration with PreservesAll[Transform] { + + override def prerequisites = Forms.LowForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.LowEmitters def collectNameMapping(namespace: Namespace, moduleNameMap: mutable.HashMap[String, String])(mod: DefModule): Unit = { val newName = namespace.newName(mod.name) diff --git a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala index c8129450..1ab60650 100644 --- a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala +++ b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala @@ -77,17 +77,15 @@ object ReplaceTruncatingArithmetic { * @note This replaces some FIRRTL primops with ops that are not actually legal FIRRTL. They are * useful for emission to languages that support non-expanding arithmetic (like Verilog) */ -class ReplaceTruncatingArithmetic extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class ReplaceTruncatingArithmetic extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(ReplaceTruncatingArithmetic.onMod(_)) diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index cc53e13d..74b291f5 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -8,6 +8,8 @@ import firrtl.Mappers._ import firrtl.annotations._ import firrtl.passes._ import firrtl.passes.memlib._ +import firrtl.stage.Forms +import firrtl.options.PreservesAll import scala.collection.mutable import AnalysisUtils._ @@ -17,9 +19,11 @@ import ResolveMaskGranularity._ /** * Lowers memories without splitting them, but without the complexity of ReplaceMemMacros */ -class SimplifyMems extends Transform { - def inputForm = MidForm - def outputForm = MidForm +class SimplifyMems extends Transform with DependencyAPIMigration with PreservesAll[Transform] { + + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = { val moduleNS = Namespace(m) @@ -76,6 +80,6 @@ class SimplifyMems extends Transform { override def execute(state: CircuitState): CircuitState = { val c = state.circuit val renames = RenameMap() - CircuitState(c.map(onModule(c, renames)), outputForm, state.annotations, Some(renames)) + state.copy(circuit = c.map(onModule(c, renames)), renames = Some(renames)) } } diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index fb6f73b4..f70e92b7 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -4,14 +4,10 @@ package TopWiring import firrtl._ import firrtl.ir._ -import firrtl.passes.{Pass, - InferTypes, - ResolveKinds, - ResolveFlows, - ExpandConnects - } +import firrtl.passes.{InferTypes, ResolveKinds, ResolveFlows, ExpandConnects} import firrtl.annotations._ import firrtl.Mappers._ +import firrtl.stage.Forms import collection.mutable @@ -33,9 +29,16 @@ case class TopWiringAnnotation(target: ComponentName, prefix: String) extends custom output files as a result of the additional ports * @note This *does* work for deduped modules */ -class TopWiringTransform extends Transform { - def inputForm: CircuitForm = MidForm - def outputForm: CircuitForm = MidForm +class TopWiringTransform extends Transform with DependencyAPIMigration { + + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters + + override def invalidates(a: Transform): Boolean = a match { + case InferTypes | ResolveKinds | ResolveFlows | ExpandConnects => true + case _ => false + } type InstPath = Seq[String] @@ -222,21 +225,6 @@ class TopWiringTransform extends Transform { } } - /** Run passes to fix up the circuit of making the new connections */ - private def fixupCircuit(circuit: Circuit): Circuit = { - val passes = Seq( - InferTypes, - ResolveKinds, - ResolveFlows, - ExpandConnects, - InferTypes, - ResolveKinds, - ResolveFlows - ) - passes.foldLeft(circuit) { case (c: Circuit, p: Pass) => p.run(c) } - } - - /** Dummy function that is currently unused. Can be used to fill an outputFunction requirment in the future */ def topWiringDummyOutputFilesFunction(dir: String, mapping: Seq[((ComponentName, Type, Boolean, InstPath, String), Int)], @@ -259,7 +247,6 @@ class TopWiringTransform extends Transform { val namespacemap = state.circuit.modules.map{ case m => (m.name -> Namespace(m)) }.toMap val modulesx = state.circuit.modules map onModule(sources, portnamesmap, instgraph, namespacemap) val newCircuit = state.circuit.copy(modules = modulesx) - val fixedCircuit = fixupCircuit(newCircuit) val mappings = sources(state.circuit.main).zipWithIndex val annosx = state.annotations.filter { @@ -267,7 +254,7 @@ class TopWiringTransform extends Transform { case _ => true } - (state.copy(circuit = fixedCircuit, annotations = annosx), mappings) + (state.copy(circuit = newCircuit, annotations = annosx), mappings) } else { (state, List.empty) } //Generate output files based on the mapping. |