diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms')
9 files changed, 34 insertions, 31 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala index 0ec4fe0b..c3c615e0 100644 --- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala +++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala @@ -819,7 +819,7 @@ class ConstantPropagation extends Transform with DependencyAPIMigration with Res } // Map from module name to component names val dontTouchMap: Map[OfModule, Set[String]] = - dontTouches.groupBy(_._1).mapValues(_.map(_._2).toSet) + dontTouches.groupBy(_._1).mapValues(_.map(_._2).toSet).toMap state.copy(circuit = run(state.circuit, dontTouchMap)) } diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 4182e496..f9e35818 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -94,7 +94,7 @@ class DeadCodeElimination extends Transform e } rec(expr) - refs + refs.toSeq } // Gets all dependencies and constructs LogicNodes from them diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 03b5faa9..30558129 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -550,7 +550,7 @@ object DedupModules extends LazyLogging { } changeInternals(rename, retype, {i => i}, {(x, y) => x}, renameExps = false)(m) - refs + refs.toIndexedSeq } def computeRenameMap(originalNames: IndexedSeq[ReferenceTarget], @@ -578,6 +578,6 @@ object DedupModules extends LazyLogging { } onExp(root) - all + all.toSeq } } diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala index 4bda25ce..b272f134 100644 --- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala +++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala @@ -107,7 +107,7 @@ object FlattenRegUpdate { } val bodyx = onStmt(mod.body) - mod.copy(body = Block(bodyx +: regUpdates)) + mod.copy(body = Block(bodyx +: regUpdates.toSeq)) } } diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 3b982fbf..166feba0 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -261,13 +261,13 @@ class GroupComponents extends Transform with DependencyAPIMigration { val topStmts = mutable.ArrayBuffer[Statement]() val group = byNode(r.name) groupStatements(group) += r mapExpr inGroupFixExps(group, topStmts) - Block(topStmts) + Block(topStmts.toSeq) case c: Connect if byNode(getWRef(c.loc).name) != "" => // Sink is in a group val topStmts = mutable.ArrayBuffer[Statement]() val group = byNode(getWRef(c.loc).name) groupStatements(group) += Connect(c.info, c.loc, inGroupFixExps(group, topStmts)(c.expr)) - Block(topStmts) + Block(topStmts.toSeq) case i: IsInvalid if byNode(getWRef(i.expr).name) != "" => // Sink is in group val group = byNode(getWRef(i.expr).name) @@ -289,7 +289,7 @@ class GroupComponents extends Transform with DependencyAPIMigration { // For all group labels (not including the original module label), return a new Module. val newModules = labelOrder.filter(_ != "") map { group => - Module(NoInfo, label2module(group), groupPorts(group).distinct, Block(groupStatements(group).distinct)) + Module(NoInfo, label2module(group), groupPorts(group).distinct.toSeq, Block(groupStatements(group).distinct.toSeq)) } Seq(m.copy(body = finalTopBody)) ++ newModules } diff --git a/src/main/scala/firrtl/transforms/InferResets.scala b/src/main/scala/firrtl/transforms/InferResets.scala index 1798e3d8..ebf1d67a 100644 --- a/src/main/scala/firrtl/transforms/InferResets.scala +++ b/src/main/scala/firrtl/transforms/InferResets.scala @@ -90,7 +90,7 @@ object InferResets { tokens.groupBy { case (TargetToken.Field(n) +: t, _) => n } .mapValues { ts => fromTokens(ts.map { case (_ +: t, tpe) => (t, tpe) }:_*) - } + }.toMap BundleTree(fields) } } @@ -281,7 +281,7 @@ class InferResets extends Transform with DependencyAPIMigration { private def makeDeclMap(map: Map[ReferenceTarget, Type]): Map[String, TypeTree] = map.groupBy(_._1.ref).mapValues { ts => TypeTree.fromTokens(ts.toSeq.map { case (target, tpe) => (target.component, tpe) }:_*) - } + }.toMap private def implPort(map: Map[String, TypeTree])(port: Port): Port = map.get(port.name) diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala index c55dab57..ea988e72 100644 --- a/src/main/scala/firrtl/transforms/ManipulateNames.scala +++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala @@ -141,17 +141,21 @@ private class RenameDataStructure( val namespaces: mutable.HashMap[CompleteTarget, Namespace] = mutable.HashMap(CircuitTarget(circuit.main) -> Namespace(circuit)) + /** Wraps a HashMap to provide better error messages when accessing a non-existing element */ + class InstanceHashMap { + type Key = ReferenceTarget + type Value = Either[ReferenceTarget, InstanceTarget] + private val m = mutable.HashMap[Key, Value]() + def apply(key: ReferenceTarget): Value = m.getOrElse(key, { + throw new FirrtlUserException( + s"""|Reference target '${key.serialize}' did not exist in mapping of reference targets to insts/mems. + | This is indicative of a circuit that has not been run through LowerTypes.""".stripMargin) + }) + def update(key: Key, value: Value): Unit = m.update(key, value) + } + /** A mapping of a reference to either an instance or a memory (encoded as a [[ReferenceTarget]] */ - val instanceMap: mutable.HashMap[ReferenceTarget, Either[ReferenceTarget, InstanceTarget]] = - new mutable.HashMap[ReferenceTarget, Either[ReferenceTarget, InstanceTarget]] { - override def apply(a: ReferenceTarget) = try { - super.apply(a) - } catch { - case t: NoSuchElementException => throw new FirrtlUserException( - s"""|Reference target '${a.serialize}' did not exist in mapping of reference targets to insts/mems. - | This is indicative of a circuit that has not been run through LowerTypes.""".stripMargin, t) - } - } + val instanceMap: InstanceHashMap = new InstanceHashMap /** Return true if a target should be skipped based on allow and block parameters */ def skip(a: Target): Boolean = block(a) || !allow(a) diff --git a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala index 6bc948cd..da803837 100644 --- a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala +++ b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala @@ -71,7 +71,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { * @param presetAnnos all the annotations * @return updated annotations */ - private def propagate(cs: CircuitState, presetAnnos: Seq[PresetAnnotation]): AnnotationSeq = { + private def propagate(cs: CircuitState, presetAnnos: Seq[PresetAnnotation], otherAnnos: Seq[Annotation]): AnnotationSeq = { val presets = presetAnnos.groupBy(_.target) // store all annotated asyncreset references val asyncToAnnotate = new TargetSet() @@ -80,7 +80,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { // store async-reset trees val asyncCoMap = new TargetSetMap() // Annotations to be appended and returned as result of the transform - val annos = cs.annotations.to[mutable.ArrayBuffer] -- presetAnnos + val newAnnos = mutable.ArrayBuffer[Annotation]() val circuitTarget = CircuitTarget(cs.circuit.main) @@ -262,7 +262,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { */ /** Annotate a given target and all its children according to the asyncCoMap */ - def annotateCo(ta: ReferenceTarget){ + def annotateCo(ta: ReferenceTarget): Unit = { if (asyncCoMap.contains(ta)){ toCleanUp += ta asyncCoMap(ta) foreach( (t: ReferenceTarget) => { @@ -278,7 +278,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { if (asyncRegMap.contains(ta)) { annotateRegSet(asyncRegMap(ta)) } else { - annos += new PresetRegAnnotation(ta) + newAnnos += PresetRegAnnotation(ta) } }) } @@ -301,7 +301,7 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { cs.circuit.foreachModule(processModule) // PHASE 1 : Initialize annotateAsyncSet(asyncToAnnotate) // PHASE 2 : Annotate - annos + otherAnnos ++ newAnnos } /* @@ -422,15 +422,14 @@ class PropagatePresetAnnotations extends Transform with DependencyAPIMigration { def execute(state: CircuitState): CircuitState = { // Collect all user-defined PresetAnnotation - val presets = state.annotations - .collect{ case m : PresetAnnotation => m } + val (presets, otherAnnos) = state.annotations.partition { case _: PresetAnnotation => true ; case _ => false } // No PresetAnnotation => no need to walk the IR - if (presets.size == 0){ + if (presets.isEmpty){ state } else { // PHASE I - Propagate - val annos = propagate(state, presets) + val annos = propagate(state, presets.asInstanceOf[Seq[PresetAnnotation]], otherAnnos) // PHASE II - CleanUp val cleanCircuit = cleanUpPresetTree(state.circuit, annos) // Because toCleanup is a class field, we need to clear it diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index 0e70ec1f..f692e513 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -51,7 +51,7 @@ class RemoveWires extends Transform with DependencyAPIMigration { e } rec(expr) - refs + refs.toSeq } // Transform netlist into DefNodes @@ -142,7 +142,7 @@ class RemoveWires extends Transform with DependencyAPIMigration { onStmt(body) getOrderedNodes(netlist, regInfo) match { case Success(logic) => - Module(info, name, ports, Block(decls ++ logic ++ otherStmts)) + Module(info, name, ports, Block(List() ++ decls ++ logic ++ otherStmts)) // If we hit a CyclicException, just abort removing wires case Failure(c: CyclicException) => val problematicNode = c.node |