diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms')
4 files changed, 66 insertions, 13 deletions
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 41ffd2be..a622feb4 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -11,6 +11,7 @@ import firrtl.analyses.InstanceKeyGraph import firrtl.Mappers._ import firrtl.Utils.{kind, throwInternalError} import firrtl.MemoizedHash._ +import firrtl.renamemap.MutableRenameMap import firrtl.backends.experimental.smt.random.DefRandom import firrtl.options.{Dependency, RegisteredTransform, ShellOption} @@ -213,7 +214,7 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend instMap: collection.Map[String, String], deadNodes: collection.Set[LogicNode], moduleMap: collection.Map[String, DefModule], - renames: RenameMap, + renames: MutableRenameMap, topName: String, doTouchExtMods: Set[String] )(mod: DefModule @@ -346,7 +347,7 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend val liveNodes = depGraph.reachableFrom(circuitSink) + circuitSink val deadNodes = depGraph.getVertices -- liveNodes - val renames = RenameMap() + val renames = MutableRenameMap() renames.setCircuit(c.main) // As we delete deadCode, we will delete ports from Modules and somtimes complete modules diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 2fb98224..373066c8 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -13,6 +13,7 @@ import firrtl.Utils.{kind, splitRef, throwInternalError} import firrtl.annotations.transforms.DupedResult import firrtl.annotations.TargetToken.{Instance, OfModule} import firrtl.options.{HasShellOptions, ShellOption} +import firrtl.renamemap.MutableRenameMap import logger.LazyLogging import scala.annotation.tailrec @@ -123,7 +124,7 @@ class DedupModules extends Transform with DependencyAPIMigration { ): (Circuit, RenameMap, AnnotationSeq) = { // RenameMap - val componentRenameMap = RenameMap() + val componentRenameMap = MutableRenameMap() componentRenameMap.setCircuit(c.main) // Maps module name to corresponding dedup module @@ -161,12 +162,12 @@ class DedupModules extends Transform with DependencyAPIMigration { logger.debug(s"[Dedup] $from -> ${to.name}") ct.module(from).asInstanceOf[CompleteTarget] -> Seq(ct.module(to.name)) } - val moduleRenameMap = RenameMap() + val moduleRenameMap = MutableRenameMap() moduleRenameMap.recordAll(map) // Build instanceify renaming map val instanceGraph = InstanceKeyGraph(c) - val instanceify = RenameMap() + val instanceify = MutableRenameMap() val moduleName2Index = c.modules .map(_.name) .zipWithIndex @@ -337,6 +338,18 @@ object DedupModules extends LazyLogging { module.map(onPort).map(onStmt) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def dedupInstances( + top: CircuitTarget, + originalModule: String, + moduleMap: Map[String, DefModule], + name2name: Map[String, String], + renameMap: RenameMap + ): DefModule = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + dedupInstances(top, originalModule, moduleMap, name2name, renameMap.asInstanceOf[MutableRenameMap]) + /** Dedup a module's instances based on dedup map * * Will fixes up module if deduped instance's ports are differently named @@ -353,7 +366,7 @@ object DedupModules extends LazyLogging { originalModule: String, moduleMap: Map[String, DefModule], name2name: Map[String, String], - renameMap: RenameMap + renameMap: MutableRenameMap ): DefModule = { val module = moduleMap(originalModule) @@ -481,11 +494,22 @@ object DedupModules extends LazyLogging { } val tag2all = hashToNames.map { case (hash, names) => hashToTag(hash) -> names.toSet } - val tagMap = RenameMap() + val tagMap = MutableRenameMap() moduleNameToTag.foreach { case (name, tag) => tagMap.record(top.module(name), top.module(tag)) } (tag2all, tagMap) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def deduplicate( + circuit: Circuit, + noDedups: Set[String], + previousDupResults: Map[String, String], + renameMap: RenameMap + ): Map[String, DefModule] = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + deduplicate(circuit, noDedups, previousDupResults, renameMap.asInstanceOf[MutableRenameMap]) + /** Deduplicate * @param circuit Circuit * @param noDedups list of modules to not dedup @@ -496,7 +520,7 @@ object DedupModules extends LazyLogging { circuit: Circuit, noDedups: Set[String], previousDupResults: Map[String, String], - renameMap: RenameMap + renameMap: MutableRenameMap ): Map[String, DefModule] = { val (moduleMap, moduleLinearization) = { @@ -587,10 +611,20 @@ object DedupModules extends LazyLogging { refs.toIndexedSeq } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") def computeRenameMap( originalNames: IndexedSeq[ReferenceTarget], dedupedNames: IndexedSeq[ReferenceTarget], renameMap: RenameMap + ): Unit = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + computeRenameMap(originalNames, dedupedNames, renameMap.asInstanceOf[MutableRenameMap]) + + def computeRenameMap( + originalNames: IndexedSeq[ReferenceTarget], + dedupedNames: IndexedSeq[ReferenceTarget], + renameMap: MutableRenameMap ): Unit = { originalNames.zip(dedupedNames).foreach { diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala index 4a796e58..3596b7e6 100644 --- a/src/main/scala/firrtl/transforms/ManipulateNames.scala +++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala @@ -5,6 +5,7 @@ package firrtl.transforms import firrtl._ import firrtl.analyses.InstanceKeyGraph import firrtl.Mappers._ +import firrtl.renamemap.MutableRenameMap import firrtl.annotations.{ CircuitTarget, @@ -24,6 +25,7 @@ import scala.collection.mutable import scala.reflect.ClassTag /** Base trait for annotations that control the behavior of transforms that sub-class ManipulateNames + * * @see [[ManipulateNamesBlocklistAnnotation]] * @see [[ManipulateNamesAllowlistAnnotation]] * @define noteLocalTargets All targets must be local. Name modification in a non-local target (e.g., a node in a @@ -141,7 +143,7 @@ case class ManipulateNamesAllowlistResultAnnotation[A <: ManipulateNames[_]]( */ private class RenameDataStructure( circuit: ir.Circuit, - val renames: RenameMap, + val renames: MutableRenameMap, val block: Target => Boolean, val allow: Target => Boolean) { @@ -399,6 +401,16 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf .map(onStatement(_: ir.Statement, r, moduleTarget)) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def run( + c: ir.Circuit, + renames: RenameMap, + block: Target => Boolean, + allow: Target => Boolean + ): ir.Circuit = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + run(c, renames.asInstanceOf[MutableRenameMap], block, allow) + /** Manipulate all names in a circuit * * @param c an input circuit @@ -409,7 +421,7 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf */ def run( c: ir.Circuit, - renames: RenameMap, + renames: MutableRenameMap, block: Target => Boolean, allow: Target => Boolean ): ir.Circuit = { @@ -485,7 +497,7 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf } } - val renames = RenameMap() + val renames = MutableRenameMap() val circuitx = run(state.circuit, renames, block, allow) val annotationsx = state.annotations.flatMap { diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index 92e19f7e..90c26efc 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -10,6 +10,7 @@ import firrtl.options.Dependency import firrtl.passes._ import firrtl.passes.memlib._ import firrtl.stage.Forms +import firrtl.renamemap.MutableRenameMap import scala.collection.mutable import AnalysisUtils._ @@ -29,7 +30,12 @@ class SimplifyMems extends Transform with DependencyAPIMigration { case _ => false } - def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = { + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = + // Cast is safe because RenameMap is sealed trait and MutableRenameMap is only subclass + onModule(c, renames.asInstanceOf[MutableRenameMap])(m) + + def onModule(c: Circuit, renames: MutableRenameMap)(m: DefModule): DefModule = { val moduleNS = Namespace(m) val connects = getConnects(m) val memAdapters = new mutable.LinkedHashMap[String, DefWire] @@ -86,7 +92,7 @@ class SimplifyMems extends Transform with DependencyAPIMigration { override def execute(state: CircuitState): CircuitState = { val c = state.circuit - val renames = RenameMap() + val renames = MutableRenameMap() state.copy(circuit = c.map(onModule(c, renames)), renames = Some(renames)) } } |