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-rw-r--r--src/main/scala/firrtl/transforms/SimplifyMems.scala8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala
index 8ecc484a..92e19f7e 100644
--- a/src/main/scala/firrtl/transforms/SimplifyMems.scala
+++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala
@@ -6,6 +6,7 @@ package transforms
import firrtl.ir._
import firrtl.Mappers._
import firrtl.annotations._
+import firrtl.options.Dependency
import firrtl.passes._
import firrtl.passes.memlib._
import firrtl.stage.Forms
@@ -21,9 +22,12 @@ import ResolveMaskGranularity._
class SimplifyMems extends Transform with DependencyAPIMigration {
override def prerequisites = Forms.MidForm
- override def optionalPrerequisites = Seq.empty
+ override def optionalPrerequisites = Seq(Dependency[InferReadWrite])
override def optionalPrerequisiteOf = Forms.MidEmitters
- override def invalidates(a: Transform) = false
+ override def invalidates(a: Transform) = a match {
+ case InferTypes => true
+ case _ => false
+ }
def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = {
val moduleNS = Namespace(m)