diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/SimplifyMems.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/SimplifyMems.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index 37302f45..a056c7da 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -9,7 +9,6 @@ import firrtl.annotations._ import firrtl.passes._ import firrtl.passes.memlib._ import firrtl.stage.Forms -import firrtl.options.PreservesAll import scala.collection.mutable import AnalysisUtils._ @@ -19,11 +18,12 @@ import ResolveMaskGranularity._ /** * Lowers memories without splitting them, but without the complexity of ReplaceMemMacros */ -class SimplifyMems extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class SimplifyMems extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty override def optionalPrerequisiteOf = Forms.MidEmitters + override def invalidates(a: Transform) = false def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = { val moduleNS = Namespace(m) |