diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala index c8129450..1ab60650 100644 --- a/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala +++ b/src/main/scala/firrtl/transforms/ReplaceTruncatingArithmetic.scala @@ -77,17 +77,15 @@ object ReplaceTruncatingArithmetic { * @note This replaces some FIRRTL primops with ops that are not actually legal FIRRTL. They are * useful for emission to languages that support non-expanding arithmetic (like Verilog) */ -class ReplaceTruncatingArithmetic extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class ReplaceTruncatingArithmetic extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(ReplaceTruncatingArithmetic.onMod(_)) |