diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/RemoveWires.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveWires.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index cfb4fc54..0504c19d 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -9,7 +9,7 @@ import firrtl.Mappers._ import firrtl.traversals.Foreachers._ import firrtl.WrappedExpression._ import firrtl.graph.{MutableDiGraph, CyclicException} -import firrtl.options.{Dependency, PreservesAll} +import firrtl.options.Dependency import scala.collection.mutable import scala.util.{Try, Success, Failure} @@ -20,7 +20,7 @@ import scala.util.{Try, Success, Failure} * wires have multiple connections that may be impossible to order in a * flow-foward way */ -class RemoveWires extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class RemoveWires extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.MidForm ++ Seq( Dependency(passes.LowerTypes), @@ -32,6 +32,8 @@ class RemoveWires extends Transform with DependencyAPIMigration with PreservesAl override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Transform) = false + // Extract all expressions that are references to a Node, Wire, or Reg // Since we are operating on LowForm, they can only be WRefs private def extractNodeWireRegRefs(expr: Expression): Seq[WRef] = { |