diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/LegalizeClocks.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/LegalizeClocks.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/LegalizeClocks.scala b/src/main/scala/firrtl/transforms/LegalizeClocks.scala index e3185deb..333eb096 100644 --- a/src/main/scala/firrtl/transforms/LegalizeClocks.scala +++ b/src/main/scala/firrtl/transforms/LegalizeClocks.scala @@ -3,7 +3,7 @@ package transforms import firrtl.ir._ import firrtl.Mappers._ -import firrtl.options.{Dependency, PreservesAll} +import firrtl.options.Dependency import firrtl.Utils.isCast // Fixup otherwise legal Verilog that lint tools and other tools don't like @@ -59,7 +59,7 @@ object LegalizeClocksTransform { } /** Ensure Clocks to be emitted are legal Verilog */ -class LegalizeClocksTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class LegalizeClocksTransform extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], @@ -72,6 +72,8 @@ class LegalizeClocksTransform extends Transform with DependencyAPIMigration with override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Transform) = false + def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(LegalizeClocksTransform.onMod(_)) state.copy(circuit = state.circuit.copy(modules = modulesx)) |