diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/LegalizeClocks.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/LegalizeClocks.scala | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/transforms/LegalizeClocks.scala b/src/main/scala/firrtl/transforms/LegalizeClocks.scala index d87cd735..2e3cb8ff 100644 --- a/src/main/scala/firrtl/transforms/LegalizeClocks.scala +++ b/src/main/scala/firrtl/transforms/LegalizeClocks.scala @@ -59,20 +59,18 @@ object LegalizeClocksTransform { } /** Ensure Clocks to be emitted are legal Verilog */ -class LegalizeClocksTransform extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class LegalizeClocksTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], Dependency[InlineBitExtractionsTransform], Dependency[InlineCastsTransform] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(LegalizeClocksTransform.onMod(_)) |