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Diffstat (limited to 'src/main/scala/firrtl/transforms/LegalizeClocks.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/LegalizeClocks.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/LegalizeClocks.scala b/src/main/scala/firrtl/transforms/LegalizeClocks.scala index 2e3cb8ff..e3185deb 100644 --- a/src/main/scala/firrtl/transforms/LegalizeClocks.scala +++ b/src/main/scala/firrtl/transforms/LegalizeClocks.scala @@ -70,7 +70,7 @@ class LegalizeClocksTransform extends Transform with DependencyAPIMigration with override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(LegalizeClocksTransform.onMod(_)) |