1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
index 3f2fcdcd..515bf407 100644
--- a/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
+++ b/src/main/scala/firrtl/transforms/InlineBitExtractions.scala
@@ -5,7 +5,7 @@ package transforms
 
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 import firrtl.PrimOps.{Bits, Head, Tail, Shr}
 import firrtl.Utils.{isBitExtract, isTemp}
 import firrtl.WrappedExpression._
@@ -94,7 +94,7 @@ object InlineBitExtractionsTransform {
 }
 
 /** Inline nodes that are simple bits */
-class InlineBitExtractionsTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class InlineBitExtractionsTransform extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
     Seq( Dependency[BlackBoxSourceHelper],
@@ -105,6 +105,8 @@ class InlineBitExtractionsTransform extends Transform with DependencyAPIMigratio
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(InlineBitExtractionsTransform.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))