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-rw-r--r--src/main/scala/firrtl/transforms/InferResets.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/InferResets.scala b/src/main/scala/firrtl/transforms/InferResets.scala
index 72724b27..4342f276 100644
--- a/src/main/scala/firrtl/transforms/InferResets.scala
+++ b/src/main/scala/firrtl/transforms/InferResets.scala
@@ -96,7 +96,7 @@ object InferResets {
}
}
-/** Infers the concrete type of [[ResetType]]s by their connections
+/** Infers the concrete type of [[firrtl.ir.ResetType ResetType]]s by their connections
*
* There are 3 cases
* 1. An abstract reset driven by and/or driving only asynchronous resets will be inferred as
@@ -105,7 +105,7 @@ object InferResets {
* error
* 1. Otherwise, the reset is inferred as synchronous (i.e. the abstract reset is only invalidated
* or is driven by or drives only synchronous resets)
- * @note This is a global inference because ports can be of type [[ResetType]]
+ * @note This is a global inference because ports can be of type [[firrtl.ir.ResetType ResetType]]
* @note This transform should be run before [[DedupModules]] so that similar Modules from
* generator languages like Chisel can infer differently
*/