aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/transforms/FlattenRegUpdate.scala')
-rw-r--r--src/main/scala/firrtl/transforms/FlattenRegUpdate.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
index f21e6b18..2bce124c 100644
--- a/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
+++ b/src/main/scala/firrtl/transforms/FlattenRegUpdate.scala
@@ -81,7 +81,8 @@ object FlattenRegUpdate {
def onStmt(stmt: Statement): Statement = stmt.map(onStmt) match {
case reg @ DefRegister(_, rname, _,_, resetCond, _) =>
- assert(resetCond == Utils.zero, "Register reset should have already been made explicit!")
+ assert(resetCond.tpe == AsyncResetType || resetCond == Utils.zero,
+ "Synchronous reset should have already been made explicit!")
val ref = WRef(reg)
val update = Connect(NoInfo, ref, constructRegUpdate(netlist.getOrElse(ref, ref)))
regUpdates += update