diff options
Diffstat (limited to 'src/main/scala/firrtl/transforms/CombineCats.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/CombineCats.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/CombineCats.scala b/src/main/scala/firrtl/transforms/CombineCats.scala index 009f52ff..7fa01e46 100644 --- a/src/main/scala/firrtl/transforms/CombineCats.scala +++ b/src/main/scala/firrtl/transforms/CombineCats.scala @@ -7,7 +7,6 @@ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.WrappedExpression._ import firrtl.annotations.NoTargetAnnotation -import firrtl.options.PreservesAll import firrtl.options.Dependency import scala.collection.mutable @@ -53,7 +52,7 @@ object CombineCats { * Use [[MaxCatLenAnnotation]] to limit the number of elements that can be concatenated. * The default maximum number of elements is 10. */ -class CombineCats extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class CombineCats extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(passes.RemoveValidIf), @@ -67,6 +66,8 @@ class CombineCats extends Transform with DependencyAPIMigration with PreservesAl Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) + override def invalidates(a: Transform) = false + val defaultMaxCatLen = 10 def execute(state: CircuitState): CircuitState = { |