1 files changed, 22 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
index d0eec02c..d2d8b449 100644
--- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala
+++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
@@ -11,6 +11,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes.{Errors, PassException}
 import firrtl.Mappers._
+import firrtl.annotations._
 import firrtl.Utils.throwInternalError
 import firrtl.graph.{MutableDiGraph,DiGraph}
 import firrtl.analyses.InstanceGraph
@@ -21,6 +22,16 @@ object CheckCombLoops {
 
 }
 
+object DontCheckCombLoopsAnnotation {
+  private val marker = "DontCheckCombLoops!"
+  private val transform = classOf[CheckCombLoops]
+  def apply(): Annotation = Annotation(CircuitTopName, transform, marker)
+  def unapply(a: Annotation): Boolean = a match {
+    case Annotation(_, targetXform, value) if targetXform == transform && value == marker => true
+    case _ => false
+  }
+}
+
 /** Finds and detects combinational logic loops in a circuit, if any
   * exist. Returns the input circuit with no modifications.
   * 
@@ -179,7 +190,7 @@ class CheckCombLoops extends Transform {
    * and only if it combinationally depends on input Y. Associate this
    * reduced graph with the module for future use.
    */
-  def run(c: Circuit): Circuit = {
+  private def run(c: Circuit): Circuit = {
     val errors = new Errors()
     /* TODO(magyar): deal with exmodules! No pass warnings currently
      *  exist. Maybe warn when iterating through modules.
@@ -210,8 +221,15 @@ class CheckCombLoops extends Transform {
   }
 
   def execute(state: CircuitState): CircuitState = {
-    val result = run(state.circuit)
-    CircuitState(result, outputForm, state.annotations, state.renames)
+    val dontRun = getMyAnnotations(state).collectFirst {
+      case DontCheckCombLoopsAnnotation() => true
+    }.getOrElse(false)
+    if (dontRun) {
+      logger.warn("Skipping Combinational Loop Detection")
+      state
+    } else {
+      val result = run(state.circuit)
+      CircuitState(result, outputForm, state.annotations, state.renames)
+    }
   }
-
 }