aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/proto
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/proto')
-rw-r--r--src/main/scala/firrtl/proto/FromProto.scala114
-rw-r--r--src/main/scala/firrtl/proto/ToProto.scala131
2 files changed, 150 insertions, 95 deletions
diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala
index 41a7e1de..5b9dd371 100644
--- a/src/main/scala/firrtl/proto/FromProto.scala
+++ b/src/main/scala/firrtl/proto/FromProto.scala
@@ -35,9 +35,9 @@ object FromProto {
// Convert from ProtoBuf message repeated Statements to FIRRRTL Block
private def compressStmts(stmts: scala.collection.Seq[ir.Statement]): ir.Statement = stmts match {
- case scala.collection.Seq() => ir.EmptyStmt
+ case scala.collection.Seq() => ir.EmptyStmt
case scala.collection.Seq(stmt) => stmt
- case multiple => ir.Block(multiple.toSeq)
+ case multiple => ir.Block(multiple.toSeq)
}
def convert(info: Firrtl.SourceInfo): ir.Info =
@@ -100,16 +100,16 @@ object FromProto {
def convert(expr: Firrtl.Expression): ir.Expression = {
import Firrtl.Expression._
expr.getExpressionCase.getNumber match {
- case REFERENCE_FIELD_NUMBER => ir.Reference(expr.getReference.getId, ir.UnknownType)
- case SUB_FIELD_FIELD_NUMBER => convert(expr.getSubField)
- case SUB_INDEX_FIELD_NUMBER => convert(expr.getSubIndex)
- case SUB_ACCESS_FIELD_NUMBER => convert(expr.getSubAccess)
- case UINT_LITERAL_FIELD_NUMBER => convert(expr.getUintLiteral)
- case SINT_LITERAL_FIELD_NUMBER => convert(expr.getSintLiteral)
+ case REFERENCE_FIELD_NUMBER => ir.Reference(expr.getReference.getId, ir.UnknownType)
+ case SUB_FIELD_FIELD_NUMBER => convert(expr.getSubField)
+ case SUB_INDEX_FIELD_NUMBER => convert(expr.getSubIndex)
+ case SUB_ACCESS_FIELD_NUMBER => convert(expr.getSubAccess)
+ case UINT_LITERAL_FIELD_NUMBER => convert(expr.getUintLiteral)
+ case SINT_LITERAL_FIELD_NUMBER => convert(expr.getSintLiteral)
case FIXED_LITERAL_FIELD_NUMBER => convert(expr.getFixedLiteral)
- case PRIM_OP_FIELD_NUMBER => convert(expr.getPrimOp)
- case MUX_FIELD_NUMBER => convert(expr.getMux)
- case VALID_IF_FIELD_NUMBER => convert(expr.getValidIf)
+ case PRIM_OP_FIELD_NUMBER => convert(expr.getPrimOp)
+ case MUX_FIELD_NUMBER => convert(expr.getMux)
+ case VALID_IF_FIELD_NUMBER => convert(expr.getValidIf)
}
}
@@ -123,8 +123,14 @@ object FromProto {
ir.DefWire(convert(info), wire.getId, convert(wire.getType))
def convert(reg: Firrtl.Statement.Register, info: Firrtl.SourceInfo): ir.DefRegister =
- ir.DefRegister(convert(info), reg.getId, convert(reg.getType), convert(reg.getClock),
- convert(reg.getReset), convert(reg.getInit))
+ ir.DefRegister(
+ convert(info),
+ reg.getId,
+ convert(reg.getType),
+ convert(reg.getClock),
+ convert(reg.getReset),
+ convert(reg.getInit)
+ )
def convert(node: Firrtl.Statement.Node, info: Firrtl.SourceInfo): ir.DefNode =
ir.DefNode(convert(info), node.getId, convert(node.getExpression))
@@ -140,8 +146,8 @@ object FromProto {
def convert(ruw: ReadUnderWrite): ir.ReadUnderWrite.Value = ruw match {
case ReadUnderWrite.UNDEFINED => ir.ReadUnderWrite.Undefined
- case ReadUnderWrite.OLD => ir.ReadUnderWrite.Old
- case ReadUnderWrite.NEW => ir.ReadUnderWrite.New
+ case ReadUnderWrite.OLD => ir.ReadUnderWrite.Old
+ case ReadUnderWrite.NEW => ir.ReadUnderWrite.New
}
def convert(dt: Firrtl.Statement.CMemory.TypeAndDepth): (ir.Type, BigInt) =
@@ -161,9 +167,9 @@ object FromProto {
import Firrtl.Statement.MemoryPort.Direction._
def convert(mportdir: Firrtl.Statement.MemoryPort.Direction): MPortDir = mportdir match {
- case MEMORY_PORT_DIRECTION_INFER => MInfer
- case MEMORY_PORT_DIRECTION_READ => MRead
- case MEMORY_PORT_DIRECTION_WRITE => MWrite
+ case MEMORY_PORT_DIRECTION_INFER => MInfer
+ case MEMORY_PORT_DIRECTION_READ => MRead
+ case MEMORY_PORT_DIRECTION_WRITE => MWrite
case MEMORY_PORT_DIRECTION_READ_WRITE => MReadWrite
}
@@ -184,12 +190,18 @@ object FromProto {
def convert(formal: Formal): ir.Formal.Value = formal match {
case Formal.ASSERT => ir.Formal.Assert
case Formal.ASSUME => ir.Formal.Assume
- case Formal.COVER => ir.Formal.Cover
+ case Formal.COVER => ir.Formal.Cover
}
def convert(ver: Firrtl.Statement.Verification, info: Firrtl.SourceInfo): ir.Verification =
- ir.Verification(convert(ver.getOp), convert(info), convert(ver.getClk),
- convert(ver.getCond), convert(ver.getEn), ir.StringLit(ver.getMsg))
+ ir.Verification(
+ convert(ver.getOp),
+ convert(info),
+ convert(ver.getClk),
+ convert(ver.getCond),
+ convert(ver.getEn),
+ ir.StringLit(ver.getMsg)
+ )
def convert(mem: Firrtl.Statement.Memory, info: Firrtl.SourceInfo): ir.DefMemory = {
val dtype = convert(mem.getType)
@@ -198,11 +210,21 @@ object FromProto {
val rws = mem.getReadwriterIdList.asScala.toSeq
import Firrtl.Statement.Memory._
val depth = mem.getDepthCase.getNumber match {
- case UINT_DEPTH_FIELD_NUMBER => BigInt(mem.getUintDepth)
+ case UINT_DEPTH_FIELD_NUMBER => BigInt(mem.getUintDepth)
case BIGINT_DEPTH_FIELD_NUMBER => convert(mem.getBigintDepth)
}
- ir.DefMemory(convert(info), mem.getId, dtype, depth, mem.getWriteLatency, mem.getReadLatency,
- rs, ws, rws, convert(mem.getReadUnderWrite))
+ ir.DefMemory(
+ convert(info),
+ mem.getId,
+ dtype,
+ depth,
+ mem.getWriteLatency,
+ mem.getReadLatency,
+ rs,
+ ws,
+ rws,
+ convert(mem.getReadUnderWrite)
+ )
}
def convert(attach: Firrtl.Statement.Attach, info: Firrtl.SourceInfo): ir.Attach = {
@@ -214,21 +236,21 @@ object FromProto {
import Firrtl.Statement._
val info = stmt.getSourceInfo
stmt.getStatementCase.getNumber match {
- case NODE_FIELD_NUMBER => convert(stmt.getNode, info)
- case CONNECT_FIELD_NUMBER => convert(stmt.getConnect, info)
+ case NODE_FIELD_NUMBER => convert(stmt.getNode, info)
+ case CONNECT_FIELD_NUMBER => convert(stmt.getConnect, info)
case PARTIAL_CONNECT_FIELD_NUMBER => convert(stmt.getPartialConnect, info)
- case WIRE_FIELD_NUMBER => convert(stmt.getWire, info)
- case REGISTER_FIELD_NUMBER => convert(stmt.getRegister, info)
- case WHEN_FIELD_NUMBER => convert(stmt.getWhen, info)
- case INSTANCE_FIELD_NUMBER => convert(stmt.getInstance, info)
- case PRINTF_FIELD_NUMBER => convert(stmt.getPrintf, info)
- case STOP_FIELD_NUMBER => convert(stmt.getStop, info)
- case MEMORY_FIELD_NUMBER => convert(stmt.getMemory, info)
+ case WIRE_FIELD_NUMBER => convert(stmt.getWire, info)
+ case REGISTER_FIELD_NUMBER => convert(stmt.getRegister, info)
+ case WHEN_FIELD_NUMBER => convert(stmt.getWhen, info)
+ case INSTANCE_FIELD_NUMBER => convert(stmt.getInstance, info)
+ case PRINTF_FIELD_NUMBER => convert(stmt.getPrintf, info)
+ case STOP_FIELD_NUMBER => convert(stmt.getStop, info)
+ case MEMORY_FIELD_NUMBER => convert(stmt.getMemory, info)
case IS_INVALID_FIELD_NUMBER =>
ir.IsInvalid(convert(info), convert(stmt.getIsInvalid.getExpression))
- case CMEMORY_FIELD_NUMBER => convert(stmt.getCmemory, info)
+ case CMEMORY_FIELD_NUMBER => convert(stmt.getCmemory, info)
case MEMORY_PORT_FIELD_NUMBER => convert(stmt.getMemoryPort, info)
- case ATTACH_FIELD_NUMBER => convert(stmt.getAttach, info)
+ case ATTACH_FIELD_NUMBER => convert(stmt.getAttach, info)
}
}
@@ -244,7 +266,7 @@ object FromProto {
val w = if (ut.hasWidth) convert(ut.getWidth) else ir.UnknownWidth
ir.UIntType(w)
}
-
+
def convert(st: Firrtl.Type.SIntType): ir.SIntType = {
val w = if (st.hasWidth) convert(st.getWidth) else ir.UnknownWidth
ir.SIntType(w)
@@ -272,13 +294,13 @@ object FromProto {
def convert(tpe: Firrtl.Type): ir.Type = {
import Firrtl.Type._
tpe.getTypeCase.getNumber match {
- case UINT_TYPE_FIELD_NUMBER => convert(tpe.getUintType)
- case SINT_TYPE_FIELD_NUMBER => convert(tpe.getSintType)
- case FIXED_TYPE_FIELD_NUMBER => convert(tpe.getFixedType)
- case CLOCK_TYPE_FIELD_NUMBER => ir.ClockType
+ case UINT_TYPE_FIELD_NUMBER => convert(tpe.getUintType)
+ case SINT_TYPE_FIELD_NUMBER => convert(tpe.getSintType)
+ case FIXED_TYPE_FIELD_NUMBER => convert(tpe.getFixedType)
+ case CLOCK_TYPE_FIELD_NUMBER => ir.ClockType
case ASYNC_RESET_TYPE_FIELD_NUMBER => ir.AsyncResetType
- case RESET_TYPE_FIELD_NUMBER => ir.ResetType
- case ANALOG_TYPE_FIELD_NUMBER => convert(tpe.getAnalogType)
+ case RESET_TYPE_FIELD_NUMBER => ir.ResetType
+ case ANALOG_TYPE_FIELD_NUMBER => convert(tpe.getAnalogType)
case BUNDLE_TYPE_FIELD_NUMBER =>
ir.BundleType(tpe.getBundleType.getFieldList.asScala.map(convert(_)).toSeq)
case VECTOR_TYPE_FIELD_NUMBER => convert(tpe.getVectorType)
@@ -287,7 +309,7 @@ object FromProto {
def convert(dir: Firrtl.Port.Direction): ir.Direction = {
dir match {
- case Firrtl.Port.Direction.PORT_DIRECTION_IN => ir.Input
+ case Firrtl.Port.Direction.PORT_DIRECTION_IN => ir.Input
case Firrtl.Port.Direction.PORT_DIRECTION_OUT => ir.Output
}
}
@@ -302,9 +324,9 @@ object FromProto {
import Firrtl.Module.ExternalModule.Parameter._
val name = param.getId
param.getValueCase.getNumber match {
- case INTEGER_FIELD_NUMBER => ir.IntParam(name, convert(param.getInteger))
- case DOUBLE_FIELD_NUMBER => ir.DoubleParam(name, param.getDouble)
- case STRING_FIELD_NUMBER => ir.StringParam(name, ir.StringLit(param.getString))
+ case INTEGER_FIELD_NUMBER => ir.IntParam(name, convert(param.getInteger))
+ case DOUBLE_FIELD_NUMBER => ir.DoubleParam(name, param.getDouble)
+ case STRING_FIELD_NUMBER => ir.StringParam(name, ir.StringLit(param.getString))
case RAW_STRING_FIELD_NUMBER => ir.RawStringParam(name, param.getRawString)
}
}
diff --git a/src/main/scala/firrtl/proto/ToProto.scala b/src/main/scala/firrtl/proto/ToProto.scala
index 47fb3cec..78b95582 100644
--- a/src/main/scala/firrtl/proto/ToProto.scala
+++ b/src/main/scala/firrtl/proto/ToProto.scala
@@ -6,7 +6,7 @@ package proto
import java.io.OutputStream
import FirrtlProtos._
-import Firrtl.Statement.{ReadUnderWrite, Formal}
+import Firrtl.Statement.{Formal, ReadUnderWrite}
import Firrtl.Expression.PrimOp.Op
import com.google.protobuf.{CodedOutputStream, WireFormat}
import firrtl.PrimOps._
@@ -15,7 +15,6 @@ import scala.collection.JavaConverters._
object ToProto {
-
/** Serialize a FIRRTL Circuit to an Output Stream as a ProtoBuf message
*
* @param ostream Output stream that will be written
@@ -38,9 +37,9 @@ object ToProto {
// Note this function is sensitive to changes to the Firrtl and Circuit protobuf message definitions
def writeToStreamFast(
ostream: OutputStream,
- info: ir.Info,
+ info: ir.Info,
modules: Seq[() => ir.DefModule],
- main: String
+ main: String
): Unit = {
val costream = CodedOutputStream.newInstance(ostream)
@@ -110,23 +109,25 @@ object ToProto {
def convert(ruw: ir.ReadUnderWrite.Value): ReadUnderWrite = ruw match {
case ir.ReadUnderWrite.Undefined => ReadUnderWrite.UNDEFINED
- case ir.ReadUnderWrite.Old => ReadUnderWrite.OLD
- case ir.ReadUnderWrite.New => ReadUnderWrite.NEW
+ case ir.ReadUnderWrite.Old => ReadUnderWrite.OLD
+ case ir.ReadUnderWrite.New => ReadUnderWrite.NEW
}
def convert(formal: ir.Formal.Value): Formal = formal match {
case ir.Formal.Assert => Formal.ASSERT
case ir.Formal.Assume => Formal.ASSUME
- case ir.Formal.Cover => Formal.COVER
+ case ir.Formal.Cover => Formal.COVER
}
def convertToIntegerLiteral(value: BigInt): Firrtl.Expression.IntegerLiteral.Builder = {
- Firrtl.Expression.IntegerLiteral.newBuilder()
+ Firrtl.Expression.IntegerLiteral
+ .newBuilder()
.setValue(value.toString)
}
def convertToBigInt(value: BigInt): Firrtl.BigInt.Builder = {
- Firrtl.BigInt.newBuilder()
+ Firrtl.BigInt
+ .newBuilder()
.setValue(com.google.protobuf.ByteString.copyFrom(value.toByteArray))
}
@@ -135,7 +136,7 @@ object ToProto {
info match {
case ir.NoInfo =>
ib.setNone(Firrtl.SourceInfo.None.newBuilder)
- case f : ir.FileInfo =>
+ case f: ir.FileInfo =>
ib.setText(f.unescaped)
// TODO properly implement MultiInfo
case ir.MultiInfo(infos) =>
@@ -148,54 +149,64 @@ object ToProto {
val eb = Firrtl.Expression.newBuilder()
expr match {
case ir.Reference(name, _, _, _) =>
- val rb = Firrtl.Expression.Reference.newBuilder()
+ val rb = Firrtl.Expression.Reference
+ .newBuilder()
.setId(name)
eb.setReference(rb)
case ir.SubField(e, name, _, _) =>
- val sb = Firrtl.Expression.SubField.newBuilder()
+ val sb = Firrtl.Expression.SubField
+ .newBuilder()
.setExpression(convert(e))
.setField(name)
eb.setSubField(sb)
case ir.SubIndex(e, value, _, _) =>
- val sb = Firrtl.Expression.SubIndex.newBuilder()
+ val sb = Firrtl.Expression.SubIndex
+ .newBuilder()
.setExpression(convert(e))
.setIndex(convertToIntegerLiteral(value))
eb.setSubIndex(sb)
case ir.SubAccess(e, index, _, _) =>
- val sb = Firrtl.Expression.SubAccess.newBuilder()
+ val sb = Firrtl.Expression.SubAccess
+ .newBuilder()
.setExpression(convert(e))
.setIndex(convert(index))
eb.setSubAccess(sb)
case ir.UIntLiteral(value, width) =>
- val ub = Firrtl.Expression.UIntLiteral.newBuilder()
+ val ub = Firrtl.Expression.UIntLiteral
+ .newBuilder()
.setValue(convertToIntegerLiteral(value))
convert(width).foreach(ub.setWidth)
eb.setUintLiteral(ub)
case ir.SIntLiteral(value, width) =>
- val sb = Firrtl.Expression.SIntLiteral.newBuilder()
+ val sb = Firrtl.Expression.SIntLiteral
+ .newBuilder()
.setValue(convertToIntegerLiteral(value))
convert(width).foreach(sb.setWidth)
eb.setSintLiteral(sb)
case ir.FixedLiteral(value, width, point) =>
- val fb = Firrtl.Expression.FixedLiteral.newBuilder()
+ val fb = Firrtl.Expression.FixedLiteral
+ .newBuilder()
.setValue(convertToBigInt(value))
convert(width).foreach(fb.setWidth)
convert(point).foreach(fb.setPoint)
eb.setFixedLiteral(fb)
case ir.DoPrim(op, args, consts, _) =>
- val db = Firrtl.Expression.PrimOp.newBuilder()
+ val db = Firrtl.Expression.PrimOp
+ .newBuilder()
.setOp(convert(op))
consts.foreach(c => db.addConst(convertToIntegerLiteral(c)))
args.foreach(a => db.addArg(convert(a)))
eb.setPrimOp(db)
case ir.Mux(cond, tval, fval, _) =>
- val mb = Firrtl.Expression.Mux.newBuilder()
+ val mb = Firrtl.Expression.Mux
+ .newBuilder()
.setCondition(convert(cond))
.setTValue(convert(tval))
.setFValue(convert(fval))
eb.setMux(mb)
case ir.ValidIf(cond, value, _) =>
- val vb = Firrtl.Expression.ValidIf.newBuilder()
+ val vb = Firrtl.Expression.ValidIf
+ .newBuilder()
.setCondition(convert(cond))
.setValue(convert(value))
eb.setValidIf(vb)
@@ -205,37 +216,41 @@ object ToProto {
def convert(dir: MPortDir): Firrtl.Statement.MemoryPort.Direction = {
import Firrtl.Statement.MemoryPort.Direction._
dir match {
- case MInfer => MEMORY_PORT_DIRECTION_INFER
- case MRead => MEMORY_PORT_DIRECTION_READ
- case MWrite => MEMORY_PORT_DIRECTION_WRITE
+ case MInfer => MEMORY_PORT_DIRECTION_INFER
+ case MRead => MEMORY_PORT_DIRECTION_READ
+ case MWrite => MEMORY_PORT_DIRECTION_WRITE
case MReadWrite => MEMORY_PORT_DIRECTION_READ_WRITE
}
}
def convert(tpe: ir.Type, depth: BigInt): Firrtl.Statement.CMemory.TypeAndDepth.Builder =
- Firrtl.Statement.CMemory.TypeAndDepth.newBuilder()
+ Firrtl.Statement.CMemory.TypeAndDepth
+ .newBuilder()
.setDataType(convert(tpe))
.setDepth(convertToBigInt(depth))
def convert(stmt: ir.Statement): Seq[Firrtl.Statement.Builder] = {
stmt match {
case ir.Block(stmts) => stmts.flatMap(convert(_))
- case ir.EmptyStmt => Seq.empty
+ case ir.EmptyStmt => Seq.empty
case other =>
val sb = Firrtl.Statement.newBuilder()
other match {
case ir.DefNode(_, name, expr) =>
- val nb = Firrtl.Statement.Node.newBuilder()
+ val nb = Firrtl.Statement.Node
+ .newBuilder()
.setId(name)
.setExpression(convert(expr))
sb.setNode(nb)
case ir.DefWire(_, name, tpe) =>
- val wb = Firrtl.Statement.Wire.newBuilder()
+ val wb = Firrtl.Statement.Wire
+ .newBuilder()
.setId(name)
.setType(convert(tpe))
sb.setWire(wb)
case ir.DefRegister(_, name, tpe, clock, reset, init) =>
- val rb = Firrtl.Statement.Register.newBuilder()
+ val rb = Firrtl.Statement.Register
+ .newBuilder()
.setId(name)
.setType(convert(tpe))
.setClock(convert(clock))
@@ -243,54 +258,63 @@ object ToProto {
.setInit(convert(init))
sb.setRegister(rb)
case ir.DefInstance(_, name, module, _) =>
- val ib = Firrtl.Statement.Instance.newBuilder()
+ val ib = Firrtl.Statement.Instance
+ .newBuilder()
.setId(name)
.setModuleId(module)
sb.setInstance(ib)
case ir.Connect(_, loc, expr) =>
- val cb = Firrtl.Statement.Connect.newBuilder()
+ val cb = Firrtl.Statement.Connect
+ .newBuilder()
.setLocation(convert(loc))
.setExpression(convert(expr))
sb.setConnect(cb)
case ir.PartialConnect(_, loc, expr) =>
- val cb = Firrtl.Statement.PartialConnect.newBuilder()
+ val cb = Firrtl.Statement.PartialConnect
+ .newBuilder()
.setLocation(convert(loc))
.setExpression(convert(expr))
sb.setPartialConnect(cb)
case ir.Conditionally(_, pred, conseq, alt) =>
val cs = convert(conseq)
val as = convert(alt)
- val wb = Firrtl.Statement.When.newBuilder()
+ val wb = Firrtl.Statement.When
+ .newBuilder()
.setPredicate(convert(pred))
cs.foreach(wb.addConsequent)
as.foreach(wb.addOtherwise)
sb.setWhen(wb)
case ir.Print(_, string, args, clk, en) =>
- val pb = Firrtl.Statement.Printf.newBuilder()
+ val pb = Firrtl.Statement.Printf
+ .newBuilder()
.setValue(string.string)
.setClk(convert(clk))
.setEn(convert(en))
args.foreach(a => pb.addArg(convert(a)))
sb.setPrintf(pb)
case ir.Stop(_, ret, clk, en) =>
- val stopb = Firrtl.Statement.Stop.newBuilder()
+ val stopb = Firrtl.Statement.Stop
+ .newBuilder()
.setReturnValue(ret)
.setClk(convert(clk))
.setEn(convert(en))
sb.setStop(stopb)
case ir.Verification(op, _, clk, cond, en, msg) =>
- val vb = Firrtl.Statement.Verification.newBuilder()
+ val vb = Firrtl.Statement.Verification
+ .newBuilder()
.setOp(convert(op))
.setClk(convert(clk))
.setCond(convert(cond))
.setEn(convert(en))
.setMsg(msg.string)
case ir.IsInvalid(_, expr) =>
- val ib = Firrtl.Statement.IsInvalid.newBuilder()
+ val ib = Firrtl.Statement.IsInvalid
+ .newBuilder()
.setExpression(convert(expr))
sb.setIsInvalid(ib)
case ir.DefMemory(_, name, dtype, depth, wlat, rlat, rs, ws, rws, ruw) =>
- val mem = Firrtl.Statement.Memory.newBuilder()
+ val mem = Firrtl.Statement.Memory
+ .newBuilder()
.setId(name)
.setType(convert(dtype))
.setBigintDepth(convertToBigInt(depth))
@@ -302,14 +326,16 @@ object ToProto {
mem.addAllReadwriterId(rws.asJava)
sb.setMemory(mem)
case CDefMemory(_, name, tpe, size, seq, ruw) =>
- val mb = Firrtl.Statement.CMemory.newBuilder()
+ val mb = Firrtl.Statement.CMemory
+ .newBuilder()
.setId(name)
.setTypeAndDepth(convert(tpe, size))
.setSyncRead(seq)
.setReadUnderWrite(convert(ruw))
sb.setCmemory(mb)
case CDefMPort(_, name, _, mem, exprs, dir) =>
- val pb = Firrtl.Statement.MemoryPort.newBuilder()
+ val pb = Firrtl.Statement.MemoryPort
+ .newBuilder()
.setId(name)
.setMemoryId(mem)
.setMemoryIndex(convert(exprs.head))
@@ -330,7 +356,8 @@ object ToProto {
}
def convert(field: ir.Field): Firrtl.Type.BundleType.Field.Builder = {
- val b = Firrtl.Type.BundleType.Field.newBuilder()
+ val b = Firrtl.Type.BundleType.Field
+ .newBuilder()
.setId(field.name)
.setIsFlipped(field.flip == ir.Flip)
.setType(convert(field.tpe))
@@ -343,12 +370,13 @@ object ToProto {
* @return Option width where None means the width field should be cleared in the parent object
*/
def convert(width: ir.Width): Option[Firrtl.Width.Builder] = width match {
- case ir.IntWidth(w) => Some(Firrtl.Width.newBuilder().setValue(w.toInt))
+ case ir.IntWidth(w) => Some(Firrtl.Width.newBuilder().setValue(w.toInt))
case ir.UnknownWidth => None
}
def convert(vtpe: ir.VectorType): Firrtl.Type.VectorType.Builder =
- Firrtl.Type.VectorType.newBuilder()
+ Firrtl.Type.VectorType
+ .newBuilder()
.setType(convert(vtpe.tpe))
.setSize(vtpe.size)
@@ -379,7 +407,7 @@ object ToProto {
tb.setResetType(rt)
case ir.AnalogType(width) =>
val at = Firrtl.Type.AnalogType.newBuilder()
- convert(width).foreach(at.setWidth)
+ convert(width).foreach(at.setWidth)
tb.setAnalogType(at)
case ir.BundleType(fields) =>
val bt = Firrtl.Type.BundleType.newBuilder()
@@ -392,12 +420,13 @@ object ToProto {
}
def convert(direction: ir.Direction): Firrtl.Port.Direction = direction match {
- case ir.Input => Firrtl.Port.Direction.PORT_DIRECTION_IN
+ case ir.Input => Firrtl.Port.Direction.PORT_DIRECTION_IN
case ir.Output => Firrtl.Port.Direction.PORT_DIRECTION_OUT
}
def convert(port: ir.Port): Firrtl.Port.Builder = {
- Firrtl.Port.newBuilder()
+ Firrtl.Port
+ .newBuilder()
.setId(port.name)
.setDirection(convert(port.direction))
.setType(convert(port.tpe))
@@ -405,7 +434,8 @@ object ToProto {
def convert(param: ir.Param): Firrtl.Module.ExternalModule.Parameter.Builder = {
import Firrtl.Module.ExternalModule._
- val pb = Parameter.newBuilder()
+ val pb = Parameter
+ .newBuilder()
.setId(param.name)
param match {
case ir.IntParam(_, value) =>
@@ -425,13 +455,15 @@ object ToProto {
module match {
case mod: ir.Module =>
val stmts = convert(mod.body)
- val mb = Firrtl.Module.UserModule.newBuilder()
+ val mb = Firrtl.Module.UserModule
+ .newBuilder()
.setId(mod.name)
ports.foreach(mb.addPort)
stmts.foreach(mb.addStatement)
b.setUserModule(mb)
case ext: ir.ExtModule =>
- val eb = Firrtl.Module.ExternalModule.newBuilder()
+ val eb = Firrtl.Module.ExternalModule
+ .newBuilder()
.setId(ext.name)
.setDefinedName(ext.defname)
ports.foreach(eb.addPort)
@@ -448,7 +480,8 @@ object ToProto {
for (m <- moduleBuilders) {
cb.addModule(m)
}
- Firrtl.newBuilder()
+ Firrtl
+ .newBuilder()
.addCircuit(cb.build())
.build()
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-08 09:57:31 +0000