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-rw-r--r--src/main/scala/firrtl/passes/Checks.scala14
-rw-r--r--src/main/scala/firrtl/passes/ExpandWhens.scala2
-rw-r--r--src/main/scala/firrtl/passes/Passes.scala44
-rw-r--r--src/main/scala/firrtl/passes/Uniquify.scala14
4 files changed, 37 insertions, 37 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 88ba6ab2..0857382b 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -69,7 +69,7 @@ object CheckHighForm extends Pass with LazyLogging {
t map (findFlip) match {
case t: BundleType => {
for (f <- t.fields) {
- if (f.flip == REVERSE) has = true
+ if (f.flip == Flip) has = true
}
t
}
@@ -366,7 +366,7 @@ object CheckTypes extends Pass with LazyLogging {
case (t:BundleType) => {
var p = true
for (x <- t.fields ) {
- if (x.flip == REVERSE) p = false
+ if (x.flip == Flip) p = false
if (!passive(x.tpe)) p = false
}
p
@@ -420,7 +420,7 @@ object CheckTypes extends Pass with LazyLogging {
e
}
- def bulk_equals (t1: Type, t2: Type, flip1: Flip, flip2: Flip): Boolean = {
+ def bulk_equals (t1: Type, t2: Type, flip1: Orientation, flip2: Orientation): Boolean = {
//;println_all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2])
(t1,t2) match {
case (ClockType, ClockType) => flip1 == flip2
@@ -448,7 +448,7 @@ object CheckTypes extends Pass with LazyLogging {
s map (check_types_e(get_info(s))) match {
case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors.append(new InvalidRegInit(s.info))
- case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
+ case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
case (s:Stop) => {
if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
@@ -517,7 +517,7 @@ object CheckGenders extends Pass {
val kindx = get_kind(e)
def flipQ (t:Type) : Boolean = {
var fQ = false
- def flip_rec (t:Type,f:Flip) : Type = {
+ def flip_rec (t:Type,f:Orientation) : Type = {
(t) match {
case (t:BundleType) => {
for (field <- t.fields) {
@@ -525,11 +525,11 @@ object CheckGenders extends Pass {
}
}
case (t:VectorType) => flip_rec(t.tpe,f)
- case (t) => if (f == REVERSE) fQ = true
+ case (t) => if (f == Flip) fQ = true
}
t
}
- flip_rec(t,DEFAULT)
+ flip_rec(t,Default)
fQ
}
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index d68b1eaa..1dac5e17 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -59,7 +59,7 @@ object ExpandWhens extends Pass {
hashx
}
private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = {
- def getGender(t: Type, i: Int, g: Gender): Gender = times(g, get_flip(t, i, DEFAULT))
+ def getGender(t: Type, i: Int, g: Gender): Gender = times(g, get_flip(t, i, Default))
val exps = create_exps(WRef(n, t, ExpKind(), g))
val expsx = ArrayBuffer[Expression]()
for (j <- 0 until exps.size) {
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index f9a79f54..0243c6cd 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -254,8 +254,8 @@ object ResolveGenders extends Pass {
case e:WSubField => {
val expx =
field_flip(tpe(e.exp),e.name) match {
- case DEFAULT => resolve_e(g)(e.exp)
- case REVERSE => resolve_e(swap(g))(e.exp)
+ case Default => resolve_e(g)(e.exp)
+ case Flip => resolve_e(swap(g))(e.exp)
}
WSubField(expx,e.name,e.tpe,g)
}
@@ -542,7 +542,7 @@ object InferWidths extends Pass {
def run (c:Circuit): Circuit = {
val v = ArrayBuffer[WGeq]()
def constrain (w1:Width,w2:Width) : Unit = v += WGeq(w1,w2)
- def get_constraints_t (t1:Type,t2:Type,f:Flip) : Unit = {
+ def get_constraints_t (t1:Type,t2:Type,f:Orientation) : Unit = {
(t1,t2) match {
case (t1:UIntType,t2:UIntType) => constrain(t1.width,t2.width)
case (t1:SIntType,t2:SIntType) => constrain(t1.width,t2.width)
@@ -566,23 +566,23 @@ object InferWidths extends Pass {
for (i <- 0 until n) {
val locx = ce_loc(i)
val expx = ce_exp(i)
- get_flip(tpe(s.loc),i,DEFAULT) match {
- case DEFAULT => constrain(width_BANG(locx),width_BANG(expx))
- case REVERSE => constrain(width_BANG(expx),width_BANG(locx)) }}
+ get_flip(tpe(s.loc),i,Default) match {
+ case Default => constrain(width_BANG(locx),width_BANG(expx))
+ case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
s }
case (s:BulkConnect) => {
- val ls = get_valid_points(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT)
+ val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
for (x <- ls) {
val locx = create_exps(s.loc)(x._1)
val expx = create_exps(s.exp)(x._2)
- get_flip(tpe(s.loc),x._1,DEFAULT) match {
- case DEFAULT => constrain(width_BANG(locx),width_BANG(expx))
- case REVERSE => constrain(width_BANG(expx),width_BANG(locx)) }}
+ get_flip(tpe(s.loc),x._1,Default) match {
+ case Default => constrain(width_BANG(locx),width_BANG(expx))
+ case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
s }
case (s:DefRegister) => {
constrain(width_BANG(s.reset),ONE)
constrain(ONE,width_BANG(s.reset))
- get_constraints_t(s.tpe,tpe(s.init),DEFAULT)
+ get_constraints_t(s.tpe,tpe(s.init),Default)
s }
case (s:Conditionally) => {
v += WGeq(width_BANG(s.pred),ONE)
@@ -708,25 +708,25 @@ object ExpandConnects extends Pass {
for (i <- 0 until n) {
val locx = locs(i)
val expx = exps(i)
- val sx = get_flip(tpe(s.loc),i,DEFAULT) match {
- case DEFAULT => Connect(s.info,locx,expx)
- case REVERSE => Connect(s.info,expx,locx)
+ val sx = get_flip(tpe(s.loc),i,Default) match {
+ case Default => Connect(s.info,locx,expx)
+ case Flip => Connect(s.info,expx,locx)
}
connects += sx
}
Begin(connects)
}
case (s:BulkConnect) => {
- val ls = get_valid_points(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT)
+ val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
val connects = ArrayBuffer[Stmt]()
val locs = create_exps(s.loc)
val exps = create_exps(s.exp)
ls.foreach { x => {
val locx = locs(x._1)
val expx = exps(x._2)
- val sx = get_flip(tpe(s.loc),x._1,DEFAULT) match {
- case DEFAULT => Connect(s.info,locx,expx)
- case REVERSE => Connect(s.info,expx,locx)
+ val sx = get_flip(tpe(s.loc),x._1,Default) match {
+ case Default => Connect(s.info,locx,expx)
+ case Flip => Connect(s.info,expx,locx)
}
connects += sx
}}
@@ -1037,9 +1037,9 @@ object CInferTypes extends Pass {
}
def to_field (p:Port) : Field = {
- if (p.direction == Output) Field(p.name,DEFAULT,p.tpe)
- else if (p.direction == Input) Field(p.name,REVERSE,p.tpe)
- else error("Shouldn't be here"); Field(p.name,REVERSE,p.tpe)
+ if (p.direction == Output) Field(p.name,Default,p.tpe)
+ else if (p.direction == Input) Field(p.name,Flip,p.tpe)
+ else error("Shouldn't be here"); Field(p.name,Flip,p.tpe)
}
def module_type (m:DefModule) : Type = BundleType(m.ports.map(p => to_field(p)))
def field_type (v:Type,s:String) : Type = {
@@ -1405,7 +1405,7 @@ object RemoveCHIRRTL extends Pass {
val rocx = remove_chirrtl_e(MALE)(s.exp)
stmts += BulkConnect(s.info,locx,rocx)
if (has_write_mport != false) {
- val ls = get_valid_points(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT)
+ val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
val locs = create_exps(get_mask(s.loc))
for (x <- ls ) {
val locx = locs(x._1)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 9f28f3fa..d0442f37 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -223,25 +223,25 @@ object Uniquify extends Pass {
def stmtToType(s: Stmt)(implicit sinfo: Info, mname: String): BundleType = {
// Recursive helper
def recStmtToType(s: Stmt): Seq[Field] = s match {
- case s: DefWire => Seq(Field(s.name, DEFAULT, s.tpe))
- case s: DefRegister => Seq(Field(s.name, DEFAULT, s.tpe))
- case s: WDefInstance => Seq(Field(s.name, DEFAULT, s.tpe))
+ case s: DefWire => Seq(Field(s.name, Default, s.tpe))
+ case s: DefRegister => Seq(Field(s.name, Default, s.tpe))
+ case s: WDefInstance => Seq(Field(s.name, Default, s.tpe))
case s: DefMemory => s.data_type match {
case (_: UIntType | _: SIntType) =>
- Seq(Field(s.name, DEFAULT, get_type(s)))
+ Seq(Field(s.name, Default, get_type(s)))
case tpe: BundleType =>
val newFields = tpe.fields map ( f =>
DefMemory(s.info, f.name, f.tpe, s.depth, s.write_latency,
s.read_latency, s.readers, s.writers, s.readwriters)
) flatMap (recStmtToType)
- Seq(Field(s.name, DEFAULT, BundleType(newFields)))
+ Seq(Field(s.name, Default, BundleType(newFields)))
case tpe: VectorType =>
val newFields = (0 until tpe.size) map ( i =>
s.copy(name = i.toString, data_type = tpe.tpe)
) flatMap (recStmtToType)
- Seq(Field(s.name, DEFAULT, BundleType(newFields)))
+ Seq(Field(s.name, Default, BundleType(newFields)))
}
- case s: DefNode => Seq(Field(s.name, DEFAULT, get_type(s)))
+ case s: DefNode => Seq(Field(s.name, Default, get_type(s)))
case s: Conditionally => recStmtToType(s.conseq) ++ recStmtToType(s.alt)
case s: Begin => (s.stmts map (recStmtToType)).flatten
case s => Seq()
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 17:45:20 +0000