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-rw-r--r--src/main/scala/firrtl/passes/wiring/WiringUtils.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index cab6aa5f..6f9b4f83 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -150,11 +150,11 @@ object WiringUtils {
* sources/sinks not under sinks/sources.
*/
if (queue.size == 1) {
- val u = queue.dequeue
+ val u = queue.dequeue()
sinkInsts.foreach { v => owners(v) = Vector(u) }
} else {
while (queue.nonEmpty) {
- val u = queue.dequeue
+ val u = queue.dequeue()
visited(u) = true
val edges = (i.graph.getEdges(u.last).map(u :+ _).toVector :+ u.dropRight(1))
@@ -222,11 +222,11 @@ object WiringUtils {
* sources/sinks not under sinks/sources.
*/
if (queue.size == 1) {
- val u = queue.dequeue
+ val u = queue.dequeue()
sinkInsts.foreach { v => owners(v) = Vector(u) }
} else {
while (queue.nonEmpty) {
- val u = queue.dequeue
+ val u = queue.dequeue()
visited(u) = true
val edges = i.graph.getEdges(u.last).map(u :+ _).toVector :+ u.dropRight(1)