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-rw-r--r--src/main/scala/firrtl/passes/CheckFlows.scala4
-rw-r--r--src/main/scala/firrtl/passes/CheckTypes.scala4
-rw-r--r--src/main/scala/firrtl/passes/ExpandWhens.scala1
3 files changed, 9 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/CheckFlows.scala b/src/main/scala/firrtl/passes/CheckFlows.scala
index b4ce4d5f..3a9cc212 100644
--- a/src/main/scala/firrtl/passes/CheckFlows.scala
+++ b/src/main/scala/firrtl/passes/CheckFlows.scala
@@ -105,6 +105,10 @@ object CheckFlows extends Pass {
case (s: Stop) =>
check_flow(info, mname, flows, SourceFlow)(s.en)
check_flow(info, mname, flows, SourceFlow)(s.clk)
+ case (s: Verification) =>
+ check_flow(info, mname, flows, SourceFlow)(s.clk)
+ check_flow(info, mname, flows, SourceFlow)(s.pred)
+ check_flow(info, mname, flows, SourceFlow)(s.en)
case _ =>
}
s foreach check_flows_e(info, mname, flows)
diff --git a/src/main/scala/firrtl/passes/CheckTypes.scala b/src/main/scala/firrtl/passes/CheckTypes.scala
index 5173b8c4..601ee524 100644
--- a/src/main/scala/firrtl/passes/CheckTypes.scala
+++ b/src/main/scala/firrtl/passes/CheckTypes.scala
@@ -310,6 +310,10 @@ object CheckTypes extends Pass {
errors.append(new PrintfArgNotGround(info, mname))
if (wt(sx.clk.tpe) != wt(ClockType)) errors.append(new ReqClk(info, mname))
if (wt(sx.en.tpe) != wt(ut)) errors.append(new EnNotUInt(info, mname))
+ case sx: Verification =>
+ if (wt(sx.clk.tpe) != wt(ClockType)) errors.append(new ReqClk(info, mname))
+ if (wt(sx.pred.tpe) != wt(ut)) errors.append(new PredNotUInt(info, mname))
+ if (wt(sx.en.tpe) != wt(ut)) errors.append(new EnNotUInt(info, mname))
case sx: DefMemory => sx.dataType match {
case AnalogType(w) => errors.append(new IllegalAnalogDeclaration(info, mname, sx.name))
case t =>
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 32fec4ed..75aad29a 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -156,6 +156,7 @@ object ExpandWhens extends Pass {
case sx: Stop =>
simlist += (if (weq(p, one)) sx else Stop(sx.info, sx.ret, sx.clk, AND(p, sx.en)))
EmptyStmt
+ case sx: Verification => if (weq(p, one)) sx else sx.copy(en = AND(p, sx.en))
// Expand conditionally, see comments below
case sx: Conditionally =>
/* 1) Recurse into conseq and alt with empty netlist, updated defaults, updated predicate