diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
12 files changed, 107 insertions, 83 deletions
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 5c9d4367..002343ac 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -5,15 +5,19 @@ package passes import firrtl.ir._ import firrtl.Mappers._ -import firrtl.Annotations._ +import firrtl.annotations._ // Datastructures import scala.collection.mutable // Tags an annotation to be consumed by this pass -case class InlineAnnotation(target: Named) extends Annotation with Loose with Unstable { - def duplicate(n: Named) = this.copy(target=n) - def transform = classOf[InlineInstances] +object InlineAnnotation { + def apply(target: Named): Annotation = Annotation(target, classOf[InlineInstances], "") + + def unapply(a: Annotation): Option[Named] = a match { + case Annotation(named, t, _) if t == classOf[InlineInstances] => Some(named) + case _ => None + } } // Only use on legal Firrtl. Specifically, the restriction of diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala index d0920406..231afbdd 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala @@ -5,7 +5,7 @@ package clocklist import firrtl._ import firrtl.ir._ -import Annotations._ +import annotations._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter, Writer} import wiring.WiringUtils.{getChildrenMap, countInstances, ChildrenMap, getLineage} diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala index b901e4e8..8b5a0627 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala @@ -5,7 +5,7 @@ package clocklist import firrtl._ import firrtl.ir._ -import Annotations._ +import annotations._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter, Writer} import wiring.WiringUtils.{getChildrenMap, countInstances, ChildrenMap, getLineage} @@ -16,17 +16,8 @@ import memlib.AnalysisUtils._ import memlib._ import Mappers._ -case class ClockListAnnotation(target: ModuleName, outputConfig: String) - extends Annotation with Loose with Unstable { - def transform = classOf[ClockListTransform] - def duplicate(n: Named) = n match { - case m: ModuleName => this.copy(target = m, outputConfig = outputConfig) - case _ => error("Clocklist can only annotate a module.") - } -} - object ClockListAnnotation { - def apply(t: String) = { + def apply(t: String): Annotation = { val usage = """ [Optional] ClockList List which signal drives each clock of every descendent of specified module @@ -55,7 +46,16 @@ Usage: case None => } val target = ModuleName(passModule, CircuitName(passCircuit)) - new ClockListAnnotation(target, outputConfig) + Annotation(target, classOf[ClockListTransform], outputConfig) + } + + def apply(target: ModuleName, outputConfig: String): Annotation = + Annotation(target, classOf[ClockListTransform], outputConfig) + + def unapply(a: Annotation): Option[(ModuleName, String)] = a match { + case Annotation(ModuleName(m, c), t, outputConfig) if t == classOf[ClockListTransform] => + Some((ModuleName(m, c), outputConfig)) + case _ => None } } diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala index 04e99d99..b81d0c7e 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala @@ -5,7 +5,7 @@ package clocklist import firrtl._ import firrtl.ir._ -import Annotations._ +import annotations._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter, Writer} import wiring.WiringUtils.{getChildrenMap, countInstances, ChildrenMap, getLineage} diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala index da1129bc..feb7f42e 100644 --- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala +++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala @@ -5,7 +5,7 @@ package clocklist import firrtl._ import firrtl.ir._ -import Annotations._ +import annotations._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter, Writer} import wiring.WiringUtils.{getChildrenMap, countInstances, ChildrenMap, getLineage} diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala index d73fbc91..668bc2e5 100644 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala @@ -4,7 +4,7 @@ package firrtl package passes package memlib import ir._ -import Annotations._ +import annotations._ import wiring._ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform { diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 6b56c5e8..2501ba04 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -11,12 +11,16 @@ import firrtl.Utils.{one, zero, BoolType} import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq -import Annotations._ +import annotations._ -case class InferReadWriteAnnotation(t: String) extends Annotation with Loose with Unstable { - val target = CircuitName(t) - def duplicate(n: Named) = this.copy(t=n.name) - def transform = classOf[InferReadWrite] +object InferReadWriteAnnotation { + def apply(t: String) = Annotation(CircuitName(t), classOf[InferReadWrite], "") + def apply(target: CircuitName) = Annotation(target, classOf[InferReadWrite], "") + def unapply(a: Annotation): Option[(CircuitName)] = a match { + case Annotation(CircuitName(t), transform, "") if transform == classOf[InferReadWrite] => + Some(CircuitName(t)) + case _ => None + } } // This pass examine the enable signals of the read & write ports of memories @@ -155,6 +159,7 @@ class InferReadWrite extends Transform with PassBased { ) def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match { case Nil => CircuitState(state.circuit, state.form) - case Seq(InferReadWriteAnnotation(_)) => CircuitState(runPasses(state.circuit), state.form) + case Seq(InferReadWriteAnnotation(CircuitName(state.circuit.main))) => + CircuitState(runPasses(state.circuit), state.form) } } diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala index 30196fad..44dad557 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala @@ -10,18 +10,17 @@ import firrtl.Mappers._ import MemPortUtils.{MemPortMap, Modules} import MemTransformUtils._ import AnalysisUtils._ -import Annotations._ +import firrtl.annotations._ import wiring._ /** Annotates the name of the pin to add for WiringTransform */ -case class PinAnnotation(target: CircuitName, pins: Seq[String]) extends Annotation with Loose with Unstable { - def transform = classOf[ReplaceMemMacros] - def duplicate(n: Named) = n match { - case n: CircuitName => this.copy(target = n) - case _ => throwInternalError +object PinAnnotation { + def apply(target: CircuitName, pins: Seq[String]): Annotation = { + Annotation(target, classOf[ReplaceMemMacros], pins.foldLeft("") { (str, p) => str + "pin:" + p + " " } ) } + val matcher = "pin:([^ ]+)".r } /** Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. @@ -220,10 +219,11 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform { writer.serialize() val pins = getMyAnnotations(state) match { case Nil => Nil - case Seq(p) => p match { - case PinAnnotation(c, pins) => pins - case _ => error(s"Bad Annotation: ${p}") - } + case Seq(Annotation(c, t, string)) => + PinAnnotation.matcher.findAllIn(string).toSeq match { + case Nil => error(s"Bad Annotation: ${Annotation(c, t, string)}") + case seq => seq + } case _ => throwInternalError } val annos = pins.foldLeft(Seq[Annotation]()) { (seq, pin) => diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index 67b81160..f8f76a49 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -5,7 +5,7 @@ package memlib import firrtl._ import firrtl.ir._ -import Annotations._ +import firrtl.annotations._ import AnalysisUtils._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter} @@ -64,9 +64,9 @@ class ConfWriter(filename: String) { } } -case class ReplSeqMemAnnotation(t: String) extends Annotation with Loose with Unstable { - - val usage = """ +object ReplSeqMemAnnotation { + def apply(t: String): Annotation = { + val usage = """ [Optional] ReplSeqMem Pass to replace sequential memories with blackboxes + configuration file @@ -82,18 +82,29 @@ Optional Arguments: -i<filename> Specify the input configuration file (for additional optimizations) """ - val passOptions = PassConfigUtil.getPassOptions(t, usage) - val outputConfig = passOptions.getOrElse( - OutputConfigFileName, - error("No output config file provided for ReplSeqMem!" + usage) - ) - val passCircuit = passOptions.getOrElse( - PassCircuitName, - error("No circuit name specified for ReplSeqMem!" + usage) - ) - val target = CircuitName(passCircuit) - def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}")) - def transform = classOf[ReplSeqMem] + val passOptions = PassConfigUtil.getPassOptions(t, usage) + val outputConfig = passOptions.getOrElse( + OutputConfigFileName, + error("No output config file provided for ReplSeqMem!" + usage) + ) + val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "") + val passCircuit = passOptions.getOrElse( + PassCircuitName, + error("No circuit name specified for ReplSeqMem!" + usage) + ) + val target = CircuitName(passCircuit) + Annotation(target, classOf[ReplSeqMem], s"$inputFileName $outputConfig") + } + + def apply(target: CircuitName, inputFileName: String, outputConfig: String): Annotation = + Annotation(target, classOf[ReplSeqMem], s"$inputFileName $outputConfig") + + private val matcher = "([^ ]*) ([^ ]+)".r + def unapply(a: Annotation): Option[(CircuitName, String, String)] = a match { + case Annotation(CircuitName(c), t, matcher(inputFileName, outputConfig)) if t == classOf[ReplSeqMem] => + Some((CircuitName(c), inputFileName, outputConfig)) + case _ => None + } } class SimpleTransform(p: Pass, form: CircuitForm) extends Transform { @@ -139,14 +150,13 @@ class ReplSeqMem extends Transform with SimpleRun { getMyAnnotations(state) match { case Nil => state.copy(annotations = None) // Do nothing if there are no annotations case p => (p.collectFirst { case a if (a.target == CircuitName(state.circuit.main)) => a }) match { - case Some(ReplSeqMemAnnotation(t)) => - val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "") + case Some(ReplSeqMemAnnotation(target, inputFileName, outputConfig)) => val inConfigFile = { if (inputFileName.isEmpty) None else if (new File(inputFileName).exists) Some(new YamlFileReader(inputFileName)) else error("Input configuration file does not exist!") } - val outConfigFile = new ConfWriter(PassConfigUtil.getPassOptions(t)(OutputConfigFileName)) + val outConfigFile = new ConfWriter(outputConfig) run(state, passSeq(inConfigFile, outConfigFile)) case _ => error("Unexpected transform annotation") } diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala index 1ced07eb..f5da4c06 100644 --- a/src/main/scala/firrtl/passes/wiring/Wiring.scala +++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala @@ -8,7 +8,8 @@ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import scala.collection.mutable -import firrtl.Annotations._ +import firrtl.annotations._ +import firrtl.annotations.AnnotationUtils._ import WiringUtils._ case class WiringException(msg: String) extends PassException(msg) diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 5c251d6d..9528c0b7 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -8,37 +8,43 @@ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import scala.collection.mutable -import firrtl.Annotations._ +import firrtl.annotations._ import WiringUtils._ /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ -case class SourceAnnotation(target: ComponentName, pin: String) extends Annotation with Loose with Unstable { - def transform = classOf[WiringTransform] - def duplicate(n: Named) = n match { - case n: ComponentName => this.copy(target = n) - case _ => throwInternalError +object SourceAnnotation { + def apply(target: ComponentName, pin: String): Annotation = Annotation(target, classOf[WiringTransform], s"source $pin") + + private val matcher = "source (.+)".r + def unapply(a: Annotation): Option[(ComponentName, String)] = a match { + case Annotation(ComponentName(n, m), _, matcher(pin)) => Some((ComponentName(n, m), pin)) + case _ => None } } /** A module, e.g. ExtModule etc., that should add the input pin */ -case class SinkAnnotation(target: ModuleName, pin: String) extends Annotation with Loose with Unstable { - def transform = classOf[WiringTransform] - def duplicate(n: Named) = n match { - case n: ModuleName => this.copy(target = n) - case _ => throwInternalError +object SinkAnnotation { + def apply(target: ModuleName, pin: String): Annotation = Annotation(target, classOf[WiringTransform], s"sink $pin") + + private val matcher = "sink (.+)".r + def unapply(a: Annotation): Option[(ModuleName, String)] = a match { + case Annotation(ModuleName(n, c), _, matcher(pin)) => Some((ModuleName(n, c), pin)) + case _ => None } } /** A module under which all sink module must be declared, and there is only * one source component */ -case class TopAnnotation(target: ModuleName, pin: String) extends Annotation with Loose with Unstable { - def transform = classOf[WiringTransform] - def duplicate(n: Named) = n match { - case n: ModuleName => this.copy(target = n) - case _ => throwInternalError +object TopAnnotation { + def apply(target: ModuleName, pin: String): Annotation = Annotation(target, classOf[WiringTransform], s"top $pin") + + private val matcher = "top (.+)".r + def unapply(a: Annotation): Option[(ModuleName, String)] = a match { + case Annotation(ModuleName(n, c), _, matcher(pin)) => Some((ModuleName(n, c), pin)) + case _ => None } } @@ -64,20 +70,18 @@ class WiringTransform extends Transform with SimpleRun { ResolveGenders) def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match { case Nil => CircuitState(state.circuit, state.form) - case p => - // Pin to value + case p => val sinks = mutable.HashMap[String, Set[String]]() val sources = mutable.HashMap[String, String]() val tops = mutable.HashMap[String, String]() val comp = mutable.HashMap[String, String]() - p.foreach { a => - a match { - case SinkAnnotation(m, pin) => sinks(pin) = sinks.getOrElse(pin, Set.empty) + m.name - case SourceAnnotation(c, pin) => - sources(pin) = c.module.name - comp(pin) = c.name - case TopAnnotation(m, pin) => tops(pin) = m.name - } + p.foreach { + case SinkAnnotation(m, pin) => + sinks(pin) = sinks.getOrElse(pin, Set.empty) + m.name + case SourceAnnotation(c, pin) => + sources(pin) = c.module.name + comp(pin) = c.name + case TopAnnotation(m, pin) => tops(pin) = m.name } (sources.size, tops.size, sinks.size, comp.size) match { case (0, 0, p, 0) => state.copy(annotations = None) diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala index 2527ccbe..29c93ca7 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala @@ -8,7 +8,7 @@ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import scala.collection.mutable -import firrtl.Annotations._ +import firrtl.annotations._ import WiringUtils._ /** Declaration kind in lineage (e.g. input port, output port, wire) |