aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/passes')
-rw-r--r--src/main/scala/firrtl/passes/PadWidths.scala5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 0b318511..163b2270 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -17,8 +17,9 @@ object PadWidths extends Pass {
((new mutable.LinkedHashSet())
++ firrtl.stage.Forms.LowForm
- Dependency(firrtl.passes.Legalize)
- + Dependency(firrtl.passes.RemoveValidIf)
- + Dependency[firrtl.transforms.ConstantPropagation]).toSeq
+ + Dependency(firrtl.passes.RemoveValidIf)).toSeq
+
+ override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation])
override val dependents =
Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays),