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-rw-r--r--src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala3
-rw-r--r--src/main/scala/firrtl/passes/memlib/InferReadWrite.scala6
-rw-r--r--src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala6
3 files changed, 11 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index 6c7b2e18..6b265239 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -14,6 +14,9 @@ import Utils._
import memlib.AnalysisUtils._
import memlib._
import Mappers._
+import firrtl.options.RegisteredTransform
+import scopt.OptionParser
+import firrtl.stage.RunFirrtlTransformAnnotation
case class ClockListAnnotation(target: ModuleName, outputConfig: String) extends
SingleTargetAnnotation[ModuleName] {
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 2d1d7f6b..c83194e8 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -12,6 +12,8 @@ import MemPortUtils.memPortField
import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin}
import WrappedExpression.weq
import annotations._
+import scopt.OptionParser
+import firrtl.stage.RunFirrtlTransformAnnotation
case object InferReadWriteAnnotation extends NoTargetAnnotation
@@ -72,10 +74,10 @@ object InferReadWritePass extends Pass {
def replaceStmt(repl: Netlist)(s: Statement): Statement =
s map replaceStmt(repl) map replaceExp(repl) match {
- case Connect(_, EmptyExpression, _) => EmptyStmt
+ case Connect(_, EmptyExpression, _) => EmptyStmt
case sx => sx
}
-
+
def inferReadWriteStmt(connects: Connects,
repl: Netlist,
stmts: Statements)
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 311813db..c49c0051 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -10,6 +10,8 @@ import AnalysisUtils._
import Utils.error
import java.io.{File, CharArrayWriter, PrintWriter}
import wiring._
+import scopt.OptionParser
+import firrtl.stage.RunFirrtlTransformAnnotation
sealed trait PassOption
case object InputConfigFileName extends PassOption
@@ -19,11 +21,11 @@ case object PassModuleName extends PassOption
object PassConfigUtil {
type PassOptionMap = Map[PassOption, String]
-
+
def getPassOptions(t: String, usage: String = "") = {
// can't use space to delimit sub arguments (otherwise, Driver.scala will throw error)
val passArgList = t.split(":").toList
-
+
def nextPassOption(map: PassOptionMap, list: List[String]): PassOptionMap = {
list match {
case Nil => map