diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/InferReadWrite.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/LowerTypes.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala index 2378216d..664b3dfc 100644 --- a/src/main/scala/firrtl/passes/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/InferReadWrite.scala @@ -139,8 +139,8 @@ object InferReadWritePass extends Pass { repl(s"${mem.name}.$w.en") = WSubField(rw_exp, "wmode", bt, FEMALE) repl(s"${mem.name}.$w.clk") = EmptyExpression repl(s"${mem.name}.$w.addr") = EmptyExpression - repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "data", mem.dataType, FEMALE) - repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "mask", ut, FEMALE) + repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "wdata", mem.dataType, FEMALE) + repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "wmask", ut, FEMALE) stmts += Connect(NoInfo, WSubField(rw_exp, "clk", ClockType, FEMALE), WRef("clk", ClockType, NodeKind(), MALE)) stmts += Connect(NoInfo, WSubField(rw_exp, "en", bt, FEMALE), diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index 7ab3333a..585598a8 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -96,7 +96,7 @@ object LowerTypes extends Pass { // Since mems with Bundle type must be split into multiple ground type // mem, references to fields addr, en, clk, and rmode must be replicated // for each resulting memory - // References to data, mask, and rdata have already been split in expand connects + // References to data, mask, rdata, wdata, and wmask have already been split in expand connects // and just need to be converted to refer to the correct new memory def lowerTypesMemExp(e: Expression): Seq[Expression] = { val (mem, port, field, tail) = splitMemRef(e) @@ -117,8 +117,8 @@ object LowerTypes extends Pass { } // Fields that need not be replicated for each // eg. mem.reader.data[0].a - // (Connect/IsInvalid must already have been split to gorund types) - } else if (Seq("data", "mask", "rdata").contains(field.name)) { + // (Connect/IsInvalid must already have been split to ground types) + } else if (Seq("data", "mask", "rdata", "wdata", "wmask").contains(field.name)) { val loMem = tail match { case Some(e) => val loMemExp = mergeRef(mem, e) diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index a8580988..1b6c76f4 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -1147,7 +1147,7 @@ object RemoveCHIRRTL extends Pass { set_poison(rws,"addr") set_wmode(rws,"wmode") set_enable(rws,"en") - set_write(rws,"data","mask") + set_write(rws,"wdata","wmask") val read_l = if (s.seq) 1 else 0 val mem = DefMemory(s.info,s.name,s.tpe,s.size,1,read_l,rds.map(_.name),wrs.map(_.name),rws.map(_.name)) Block(Seq(mem,Block(stmts))) @@ -1160,11 +1160,11 @@ object RemoveCHIRRTL extends Pass { val masks = ArrayBuffer[String]() s.direction match { case MReadWrite => { - repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"rdata","data","mask",true) + repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"rdata","wdata","wmask",true) addrs += "addr" clks += "clk" ens += "en" - masks += "mask" + masks += "wmask" } case MWrite => { repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"data","data","mask",false) |