diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
14 files changed, 69 insertions, 60 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 02d35740..dad0f69c 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -73,7 +73,7 @@ object CheckWidths extends Pass { (w, t) match { case (IntWidth(width), _) if width >= MaxWidth => errors.append(new WidthTooBig(info, target.serialize, width)) - case (w: IntWidth, f: FixedType) if (w.width < 0 && w.width == f.width) => + case (w: IntWidth, f: FixedType) if (w.width < 0 && w.width == f.width.asInstanceOf[IntWidth].width) => errors.append(new NegWidthException(info, target.serialize)) case (_: IntWidth, _) => case _ => diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 8fb4e5fb..1fd79f3a 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -125,13 +125,22 @@ object ExpandWhens extends Pass { EmptyStmt // For simulation constructs, update simlist with predicated statement and return EmptyStmt case sx: Print => - simlist += (if (weq(p, one)) sx else sx.withEn(AND(p, sx.en))) + simlist += (if (weq(p, one)) sx else sx match { + case s: Print => s.copy(en = AND(p, s.en)) + case o => o + }) EmptyStmt case sx: Stop => - simlist += (if (weq(p, one)) sx else sx.withEn(AND(p, sx.en))) + simlist += (if (weq(p, one)) sx else sx match { + case s: Stop => s.copy(en = AND(p, s.en)) + case o => o + }) EmptyStmt case sx: Verification => - simlist += (if (weq(p, one)) sx else sx.withEn(AND(p, sx.en))) + simlist += (if (weq(p, one)) sx else sx match { + case s: Verification => s.copy(en = AND(p, s.en)) + case o => o + }) EmptyStmt // Expand conditionally, see comments below case sx: Conditionally => diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala index 8ab78fee..b1910831 100644 --- a/src/main/scala/firrtl/passes/InferTypes.scala +++ b/src/main/scala/firrtl/passes/InferTypes.scala @@ -41,7 +41,7 @@ object InferTypes extends Pass { // we first need to remove the unknown widths and bounds from all ports, // as their type will determine the module types - val portsKnown = c.modules.map(_.map { p: Port => p.copy(tpe = remove_unknowns(p.tpe)) }) + val portsKnown = c.modules.map(_.map { (p: Port) => p.copy(tpe = remove_unknowns(p.tpe)) }) val mtypes = portsKnown.map(m => m.name -> module_type(m)).toMap def infer_types_e(types: TypeLookup)(e: Expression): Expression = diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala index d0677fad..b3ef569a 100644 --- a/src/main/scala/firrtl/passes/InferWidths.scala +++ b/src/main/scala/firrtl/passes/InferWidths.scala @@ -31,7 +31,7 @@ case class WidthGeqConstraintAnnotation(loc: ReferenceTarget, exp: ReferenceTarg "is not supported by WidthGeqConstraintAnnotation\n" + target.prettyPrint() ) } - } + }: @unchecked (newLoc, newExp) match { case (Some(l: ReferenceTarget), Some(e: ReferenceTarget)) => Seq(WidthGeqConstraintAnnotation(l, e)) @@ -265,7 +265,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths with Dependency } leafType - } + }: @unchecked //get_constraints_t(locType, expType) addTypeConstraints(anno.loc, anno.exp)(locType, expType) diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index e2105ff2..496b4ecf 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -244,7 +244,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe * The [[RenameMap]]s in renamesMap are appear in renamesSeq * in the order that they should be applied */ - val (renamesMap, renamesSeq) = { + val (renamesMap, renamesSeq): (Map[(OfModule, Instance), MutableRenameMap], Seq[RenameMap]) = {{ val mutableDiGraph = new MutableDiGraph[(OfModule, Instance)] // compute instance graph instMaps.foreach { @@ -284,7 +284,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe val resultMap = indexMap.mapValues(idx => resultSeq(maxIdx - idx)) (resultMap, resultSeq) } - } + }}: @unchecked def fixupRefs( instMap: collection.Map[Instance, OfModule], @@ -369,7 +369,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe }) // Upcast so reduce works (andThen returns RenameMap) - val renames = (renamesSeq: Seq[RenameMap]).reduceLeftOption(_ andThen _) + val renames = (renamesSeq: Seq[RenameMap]).reduceLeftOption(_ `andThen` _) val cleanedAnnos = annos.filterNot { case InlineAnnotation(_) => true diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index 976741fd..7bec15fc 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -25,6 +25,7 @@ import firrtl.{ UnknownForm, Utils } +import firrtl.{seqToAnnoSeq, annoSeqToSeq} import firrtl.ir._ import firrtl.options.Dependency import firrtl.stage.TransformManager.TransformDependency diff --git a/src/main/scala/firrtl/passes/ResolveKinds.scala b/src/main/scala/firrtl/passes/ResolveKinds.scala index 745be1e2..e3218467 100644 --- a/src/main/scala/firrtl/passes/ResolveKinds.scala +++ b/src/main/scala/firrtl/passes/ResolveKinds.scala @@ -5,7 +5,6 @@ package firrtl.passes import firrtl._ import firrtl.ir._ import firrtl.Mappers._ -import firrtl.backends.experimental.smt.random.DefRandom import firrtl.traversals.Foreachers._ object ResolveKinds extends Pass { @@ -32,7 +31,6 @@ object ResolveKinds extends Pass { case sx: DefRegister => kinds(sx.name) = RegKind case sx: WDefInstance => kinds(sx.name) = InstanceKind case sx: DefMemory => kinds(sx.name) = MemKind - case sx: DefRandom => kinds(sx.name) = RandomKind case _ => } s.map(resolve_stmt(kinds)) diff --git a/src/main/scala/firrtl/passes/TrimIntervals.scala b/src/main/scala/firrtl/passes/TrimIntervals.scala index 99a97a38..bb927381 100644 --- a/src/main/scala/firrtl/passes/TrimIntervals.scala +++ b/src/main/scala/firrtl/passes/TrimIntervals.scala @@ -76,10 +76,10 @@ class TrimIntervals extends Pass { case DoPrim(o, args, consts, t) if opsToFix.contains(o) && (args.map(_.tpe).collect { case x: IntervalType => x }).size == args.size => - val maxBP = args.map(_.tpe).collect { case IntervalType(_, _, p) => p }.reduce(_ max _) + val maxBP = args.map(_.tpe).collect { case IntervalType(_, _, p) => p }.reduce(_ `max` _) DoPrim(o, args.map { a => fixBP(maxBP)(a) }, consts, t) case Mux(cond, tval, fval, t: IntervalType) => - val maxBP = Seq(tval, fval).map(_.tpe).collect { case IntervalType(_, _, p) => p }.reduce(_ max _) + val maxBP = Seq(tval, fval).map(_.tpe).collect { case IntervalType(_, _, p) => p }.reduce(_ `max` _) Mux(cond, fixBP(maxBP)(tval), fixBP(maxBP)(fval), t) case other => other } diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala index 2bd17519..358c34e2 100644 --- a/src/main/scala/firrtl/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl/passes/VerilogPrep.scala @@ -32,7 +32,7 @@ object VerilogPrep extends Pass { Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl.transforms.FlattenRegUpdate], Dependency(passes.VerilogModulusCleanup), - Dependency[firrtl.transforms.VerilogRename] + Dependency[firrtl.transforms.VerilogRename[?]] ) override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized diff --git a/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala b/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala index 240c2c9a..c2d7a6f1 100644 --- a/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala +++ b/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala @@ -22,8 +22,9 @@ class CreateMemoryAnnotations extends Transform with DependencyAPIMigration { Seq(MemLibOutConfigFileAnnotation(outputConfig, Nil)) ++ { if (inputFileName.isEmpty) None else if (new File(inputFileName).exists) { - import CustomYAMLProtocol._ - Some(PinAnnotation(new YamlFileReader(inputFileName).parse[Config].map(_.pin.name))) + error("custom yaml protocol not supported in scala 3") + // import CustomYAMLProtocol._ + // Some(PinAnnotation(new YamlFileReader(inputFileName).parse[Config].map(_.pin.name))) } else error("Input configuration file does not exist!") } case a => Seq(a) diff --git a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala index 186ca78c..f19db4e5 100644 --- a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala +++ b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala @@ -7,7 +7,7 @@ import firrtl.options.{RegisteredLibrary, ShellOption} class MemLibOptions extends RegisteredLibrary { val name: String = "MemLib Options" - val options: Seq[ShellOption[_]] = Seq(new InferReadWrite, new ReplSeqMem) + val options: Seq[ShellOption[?]] = Seq(new InferReadWrite, new ReplSeqMem) .flatMap(_.options) } diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala index 7a1a57fb..add05fe2 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala @@ -90,7 +90,7 @@ object ResolveMaskGranularity extends Pass { */ def getMaskBits(connects: Connects, wen: Expression, wmask: Expression): Option[Int] = { val wenOrigin = getOrigin(connects)(wen) - val wmaskOrigin = connects.keys.filter(_.startsWith(wmask.serialize)).map { s: String => getOrigin(connects, s) } + val wmaskOrigin = connects.keys.filter(_.startsWith(wmask.serialize)).map { (s: String) => getOrigin(connects, s) } // all wmask bits are equal to wmode/wen or all wmask bits = 1(for redundancy checking) val redundantMask = wmaskOrigin.forall(x => weq(x, wenOrigin) || weq(x, one)) if (redundantMask) None else Some(wmaskOrigin.size) diff --git a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala index 99344973..fbb25656 100644 --- a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala @@ -1,45 +1,45 @@ -// SPDX-License-Identifier: Apache-2.0 +// // SPDX-License-Identifier: Apache-2.0 -package firrtl.passes -package memlib -import net.jcazevedo.moultingyaml._ -import java.io.{CharArrayWriter, File, PrintWriter} -import firrtl.FileUtils +// package firrtl.passes +// package memlib +// import net.jcazevedo.moultingyaml._ +// import java.io.{CharArrayWriter, File, PrintWriter} +// import firrtl.FileUtils -object CustomYAMLProtocol extends DefaultYamlProtocol { - // bottom depends on top - implicit val _pin = yamlFormat1(Pin) - implicit val _source = yamlFormat2(Source) - implicit val _top = yamlFormat1(Top) - implicit val _configs = yamlFormat3(Config) -} +// object CustomYAMLProtocol extends DefaultYamlProtocol { +// // bottom depends on top +// implicit val _pin = yamlFormat1(Pin) +// implicit val _source = yamlFormat2(Source) +// implicit val _top = yamlFormat1(Top) +// implicit val _configs = yamlFormat3(Config) +// } -case class Pin(name: String) -case class Source(name: String, module: String) -case class Top(name: String) -case class Config(pin: Pin, source: Source, top: Top) +// case class Pin(name: String) +// case class Source(name: String, module: String) +// case class Top(name: String) +// case class Config(pin: Pin, source: Source, top: Top) -class YamlFileReader(file: String) { - def parse[A](implicit reader: YamlReader[A]): Seq[A] = { - if (new File(file).exists) { - val yamlString = FileUtils.getText(file) - yamlString.parseYamls.flatMap(x => - try Some(reader.read(x)) - catch { case e: Exception => None } - ) - } else sys.error("Yaml file doesn't exist!") - } -} +// class YamlFileReader(file: String) { +// def parse[A](implicit reader: YamlReader[A]): Seq[A] = { +// if (new File(file).exists) { +// val yamlString = FileUtils.getText(file) +// yamlString.parseYamls.flatMap(x => +// try Some(reader.read(x)) +// catch { case e: Exception => None } +// ) +// } else sys.error("Yaml file doesn't exist!") +// } +// } -class YamlFileWriter(file: String) { - val outputBuffer = new CharArrayWriter - val separator = "--- \n" - def append(in: YamlValue): Unit = { - outputBuffer.append(s"$separator${in.prettyPrint}") - } - def dump(): Unit = { - val outputFile = new PrintWriter(file) - outputFile.write(outputBuffer.toString) - outputFile.close() - } -} +// class YamlFileWriter(file: String) { +// val outputBuffer = new CharArrayWriter +// val separator = "--- \n" +// def append(in: YamlValue): Unit = { +// outputBuffer.append(s"$separator${in.prettyPrint}") +// } +// def dump(): Unit = { +// val outputFile = new PrintWriter(file) +// outputFile.write(outputBuffer.toString) +// outputFile.close() +// } +// } diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala index 45eb61bf..c5faefac 100644 --- a/src/main/scala/firrtl/passes/wiring/Wiring.scala +++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala @@ -50,7 +50,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { portNames(i) = portNames(i) + (m.name -> { if (si.exists(getModuleName(_) == m.name)) ns.newName(p) - else ns.newName(tokenize(c).filterNot("[]." contains _).mkString("_")) + else ns.newName(tokenize(c).filterNot("[]." `contains` _).mkString("_")) }) } } |