diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo | bin | 20480 -> 0 bytes | |||
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 1 |
3 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo b/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo Binary files differdeleted file mode 100644 index abd7c349..00000000 --- a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo +++ /dev/null diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index ffdea1f2..28291135 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -26,6 +26,7 @@ MODIFICATIONS. */ package firrtl.passes +package memlib import firrtl._ import firrtl.ir._ diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 2f7126b4..3aa63942 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -26,6 +26,7 @@ MODIFICATIONS. */ package firrtl.passes +package memlib import firrtl._ import firrtl.ir._ |