diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
10 files changed, 12 insertions, 21 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index e28116ea..c1415b19 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -397,7 +397,7 @@ object CheckTypes extends Pass { case (_: AnalogType, _: AnalogType) => true case (t1: BundleType, t2: BundleType) => val t1_fields = (t1.fields foldLeft Map[String, (Type, Orientation)]())( - (map, f1) => map + (f1.name -> (f1.tpe, f1.flip))) + (map, f1) => map + (f1.name ->( (f1.tpe, f1.flip) ))) t2.fields forall (f2 => t1_fields get f2.name match { case None => true diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala index 24482076..288b62ba 100644 --- a/src/main/scala/firrtl/passes/InferTypes.scala +++ b/src/main/scala/firrtl/passes/InferTypes.scala @@ -78,7 +78,6 @@ object CInferTypes extends Pass { type TypeMap = collection.mutable.LinkedHashMap[String, Type] def run(c: Circuit): Circuit = { - val namespace = Namespace() val mtypes = (c.modules map (m => m.name -> module_type(m))).toMap def infer_types_e(types: TypeMap)(e: Expression) : Expression = diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala index 79dda51b..cf6f2ae0 100644 --- a/src/main/scala/firrtl/passes/InferWidths.scala +++ b/src/main/scala/firrtl/passes/InferWidths.scala @@ -288,7 +288,6 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { def get_constraints_s(s: Statement): Unit = { s map get_constraints_declared_type match { case (s: Connect) => - val n = get_size(s.loc.tpe) val locs = create_exps(s.loc) val exps = create_exps(s.expr) v ++= locs.zip(exps).flatMap { case (locx, expx) => diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 986252ea..7f8913c6 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -45,7 +45,7 @@ class InlineInstances extends Transform with RegisteredTransform { helpValueName = Some("<circuit>[.<module>[.<instance>]][,...]") ) ) private def collectAnns(circuit: Circuit, anns: Iterable[Annotation]): (Set[ModuleName], Set[ComponentName]) = - anns.foldLeft(Set.empty[ModuleName], Set.empty[ComponentName]) { + anns.foldLeft( (Set.empty[ModuleName], Set.empty[ComponentName]) ) { case ((modNames, instNames), ann) => ann match { case InlineAnnotation(CircuitName(c)) => (circuit.modules.collect { diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala index aa20e41e..412098fd 100644 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala @@ -3,8 +3,6 @@ package firrtl package passes package memlib -import annotations._ -import wiring._ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform { def inputForm = MidForm @@ -14,10 +12,8 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform case Some(r) => import CustomYAMLProtocol._ val configs = r.parse[Config] - val cN = CircuitName(state.circuit.main) val oldAnnos = state.annotations val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { case ((annos, pins), config) => - val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), config.pin.name) (annos, pins :+ config.pin.name) } state.copy(annotations = PinAnnotation(pins.toSeq) +: as) diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 1663efaa..44f45985 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -85,8 +85,6 @@ object InferReadWritePass extends Pass { (s: Statement): Statement = s match { // infer readwrite ports only for non combinational memories case mem: DefMemory if mem.readLatency > 0 => - val ut = UnknownType - val ug = UNKNOWNGENDER val readers = new PortSet val writers = new PortSet val readwriters = collection.mutable.ArrayBuffer[String]() diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala index aa60fca0..2379feab 100644 --- a/src/main/scala/firrtl/passes/memlib/MemIR.scala +++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala @@ -3,7 +3,6 @@ package firrtl.passes package memlib -import firrtl._ import firrtl.ir._ object DefAnnotatedMemory { diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index f06ca61a..10bcadfb 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -41,7 +41,7 @@ object VerilogMemDelays extends Pass { if !ports(newName) } yield newName).head val rwMap = (sx.readwriters map (rw => - rw -> (newPortName(rw, "r"), newPortName(rw, "w")))).toMap + rw ->( (newPortName(rw, "r"), newPortName(rw, "w")) ))).toMap // 1. readwrite ports are split into read & write ports // 2. memories are transformed into combinational // because latency pipes are added for longer latencies @@ -59,7 +59,7 @@ object VerilogMemDelays extends Pass { // 2) pipe registers and connects val node = DefNode(NoInfo, namespace.newTemp, netlist(e)) val wref = WRef(node.name, e.tpe, NodeKind, MALE) - ((0 until n) foldLeft (wref, Seq[Statement](node))){case ((ex, stmts), i) => + ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) => val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i" val exx = WRef(name, e.tpe, RegKind, ug) (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++ diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala index 447a5a6a..c074168b 100644 --- a/src/main/scala/firrtl/passes/wiring/Wiring.scala +++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala @@ -97,7 +97,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val from = s"${portNames(pm)}" meta(pm) = meta(pm).copy( addPortOrWire = Some((portNames(pm), DecWire)), - cons = (meta(pm).cons :+ (to, from)).distinct + cons = (meta(pm).cons :+( (to, from) )).distinct ) meta(cm) = meta(cm).copy( addPortOrWire = Some((portNames(cm), DecInput)) @@ -115,7 +115,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val from = s"$ci.${portNames(cm)}" meta(pm) = meta(pm).copy( addPortOrWire = Some((portNames(pm), DecWire)), - cons = (meta(pm).cons :+ (to, from)).distinct + cons = (meta(pm).cons :+( (to, from) )).distinct ) } } @@ -126,7 +126,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val from = s"${portNames(m)}" sinkComponents(m).foreach( to => meta(m) = meta(m).copy( - cons = (meta(m).cons :+ (to, from)).distinct + cons = (meta(m).cons :+( (to, from) )).distinct ) ) } @@ -137,7 +137,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val to = s"${portNames(m)}" val from = compName meta(m) = meta(m).copy( - cons = (meta(m).cons :+ (to, from)).distinct + cons = (meta(m).cons :+( (to, from) )).distinct ) } @@ -147,7 +147,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val to = s"${portNames(pm)}" val from = s"$ci.${portNames(cm)}" meta(pm) = meta(pm).copy( - cons = (meta(pm).cons :+ (to, from)).distinct + cons = (meta(pm).cons :+( (to, from) )).distinct ) meta(cm) = meta(cm).copy( addPortOrWire = Some((portNames(cm), DecOutput)) @@ -163,7 +163,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { val to = s"$ci.${portNames(cm)}" val from = s"${portNames(pm)}" meta(pm) = meta(pm).copy( - cons = (meta(pm).cons :+ (to, from)).distinct + cons = (meta(pm).cons :+( (to, from) )).distinct ) } } diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala index 45cf1212..9eed358f 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala @@ -85,9 +85,9 @@ object WiringUtils { val childrenMap = new ChildrenMap() def getChildren(mname: String)(s: Statement): Unit = s match { case s: WDefInstance => - childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module) + childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) ) case s: DefInstance => - childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module) + childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) ) case s => s.foreach(getChildren(mname)) } c.modules.foreach{ m => |