diff options
Diffstat (limited to 'src/main/scala/firrtl/passes')
25 files changed, 25 insertions, 25 deletions
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala index 08c127da..355f728e 100644 --- a/src/main/scala/firrtl/passes/CheckChirrtl.scala +++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala @@ -8,7 +8,7 @@ import firrtl.options.{Dependency, PreservesAll} object CheckChirrtl extends Pass with CheckHighFormLike with PreservesAll[Transform] { - override val dependents = firrtl.stage.Forms.ChirrtlForm ++ + override val optionalPrerequisiteOf = firrtl.stage.Forms.ChirrtlForm ++ Seq( Dependency(CInferTypes), Dependency(CInferMDir), Dependency(RemoveCHIRRTL) ) diff --git a/src/main/scala/firrtl/passes/CheckFlows.scala b/src/main/scala/firrtl/passes/CheckFlows.scala index bd637ff0..3fdb3443 100644 --- a/src/main/scala/firrtl/passes/CheckFlows.scala +++ b/src/main/scala/firrtl/passes/CheckFlows.scala @@ -12,7 +12,7 @@ object CheckFlows extends Pass with PreservesAll[Transform] { override def prerequisites = Dependency(passes.ResolveFlows) +: firrtl.stage.Forms.WorkingIR - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency[passes.InferBinaryPoints], Dependency[passes.TrimIntervals], Dependency[passes.InferWidths], diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala index 51b9c6f0..25bfc20b 100644 --- a/src/main/scala/firrtl/passes/CheckHighForm.scala +++ b/src/main/scala/firrtl/passes/CheckHighForm.scala @@ -285,7 +285,7 @@ object CheckHighForm extends Pass with CheckHighFormLike with PreservesAll[Trans override def prerequisites = firrtl.stage.Forms.WorkingIR - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency(passes.ResolveKinds), Dependency(passes.InferTypes), Dependency(passes.Uniquify), diff --git a/src/main/scala/firrtl/passes/CheckTypes.scala b/src/main/scala/firrtl/passes/CheckTypes.scala index eecc692e..702e7355 100644 --- a/src/main/scala/firrtl/passes/CheckTypes.scala +++ b/src/main/scala/firrtl/passes/CheckTypes.scala @@ -15,7 +15,7 @@ object CheckTypes extends Pass with PreservesAll[Transform] { override def prerequisites = Dependency(InferTypes) +: firrtl.stage.Forms.WorkingIR - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency(passes.Uniquify), Dependency(passes.ResolveFlows), Dependency(passes.CheckFlows), diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 6761bc7d..3c7ad0a8 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -15,7 +15,7 @@ object CheckWidths extends Pass with PreservesAll[Transform] { override def prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR - override def dependents = Seq(Dependency[transforms.InferResets]) + override def optionalPrerequisiteOf = Seq(Dependency[transforms.InferResets]) /** The maximum allowed width for any circuit element */ val MaxWidth = 1000000 diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala index 100b3187..567cf5f1 100644 --- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala +++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala @@ -16,7 +16,7 @@ object CommonSubexpressionElimination extends Pass with PreservesAll[Transform] Dependency(firrtl.passes.SplitExpressions), Dependency[firrtl.transforms.CombineCats] ) - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) diff --git a/src/main/scala/firrtl/passes/InferBinaryPoints.scala b/src/main/scala/firrtl/passes/InferBinaryPoints.scala index ab08926c..a3e832f0 100644 --- a/src/main/scala/firrtl/passes/InferBinaryPoints.scala +++ b/src/main/scala/firrtl/passes/InferBinaryPoints.scala @@ -18,7 +18,7 @@ class InferBinaryPoints extends Pass with PreservesAll[Transform] { Dependency(Uniquify), Dependency(ResolveFlows) ) - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty private val constraintSolver = new ConstraintSolver() diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 047703da..ec674c19 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -28,7 +28,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe override def prerequisites = Forms.LowForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.LowEmitters + override def optionalPrerequisiteOf = Forms.LowEmitters override def invalidates(a: Transform): Boolean = a == ResolveKinds diff --git a/src/main/scala/firrtl/passes/Legalize.scala b/src/main/scala/firrtl/passes/Legalize.scala index 6f0e23f1..7a59605a 100644 --- a/src/main/scala/firrtl/passes/Legalize.scala +++ b/src/main/scala/firrtl/passes/Legalize.scala @@ -16,7 +16,7 @@ object Legalize extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = Seq.empty - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty private def legalizeShiftRight(e: DoPrim): Expression = { require(e.op == Shr) diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index 8168b665..4a87ff8b 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -26,7 +26,7 @@ object LowerTypes extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.MidForm - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty override def invalidates(a: Transform): Boolean = a match { case ResolveKinds | InferTypes | ResolveFlows | _: InferWidths => true diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 22dde436..ca5c2544 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -21,7 +21,7 @@ object PadWidths extends Pass { override def optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation]) - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) diff --git a/src/main/scala/firrtl/passes/RemoveEmpty.scala b/src/main/scala/firrtl/passes/RemoveEmpty.scala index 5951b5c0..2407acb6 100644 --- a/src/main/scala/firrtl/passes/RemoveEmpty.scala +++ b/src/main/scala/firrtl/passes/RemoveEmpty.scala @@ -11,7 +11,7 @@ object RemoveEmpty extends Pass with DependencyAPIMigration with PreservesAll[Tr override def prerequisites = Seq.empty override def optionalPrerequisites = Forms.LowFormOptimized - override def dependents = Forms.ChirrtlEmitters + override def optionalPrerequisiteOf = Forms.ChirrtlEmitters private def onModule(m: DefModule): DefModule = { m match { diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index 70a575ad..895cb10f 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -31,7 +31,7 @@ object RemoveValidIf extends Pass { override def prerequisites = firrtl.stage.Forms.LowForm - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index 808f9f0d..7124111b 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -20,7 +20,7 @@ object SplitExpressions extends Pass with PreservesAll[Transform] { Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency(firrtl.passes.memlib.VerilogMemDelays) ) - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) diff --git a/src/main/scala/firrtl/passes/TrimIntervals.scala b/src/main/scala/firrtl/passes/TrimIntervals.scala index 65a43787..50da2323 100644 --- a/src/main/scala/firrtl/passes/TrimIntervals.scala +++ b/src/main/scala/firrtl/passes/TrimIntervals.scala @@ -29,7 +29,7 @@ class TrimIntervals extends Pass with PreservesAll[Transform] { Dependency(ResolveFlows), Dependency[InferBinaryPoints] ) - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty def run(c: Circuit): Circuit = { // Open -> closed diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index f063fccf..6debaf93 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -37,7 +37,7 @@ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty private def onModule(m: Module): Module = { val namespace = Namespace(m) diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala index 6733e9d5..9f5de84e 100644 --- a/src/main/scala/firrtl/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl/passes/VerilogPrep.scala @@ -33,7 +33,7 @@ object VerilogPrep extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty type AttachSourceMap = Map[WrappedExpression, Expression] diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala index b097d748..e6617857 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala @@ -55,7 +55,7 @@ class ClockListTransform extends Transform with DependencyAPIMigration with Regi override def prerequisites = Forms.LowForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.LowEmitters + override def optionalPrerequisiteOf = Forms.LowEmitters val options = Seq( new ShellOption[String]( diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala index 48e8041a..7d537387 100644 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala @@ -13,7 +13,7 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters def execute(state: CircuitState): CircuitState = reader match { case None => state diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 0de2f46d..ddcf9483 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -152,7 +152,7 @@ class InferReadWrite extends Transform override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters val options = Seq( new ShellOption[Unit]( diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala index abc145f0..f14a793e 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala @@ -30,7 +30,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters /** Return true if mask granularity is per bit, false if per byte or unspecified */ diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index f5030188..fe470ef9 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -107,7 +107,7 @@ class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigrat override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters val options = Seq( new ShellOption[String]( diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala index 007aa330..e64f6cd9 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala @@ -20,7 +20,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration with override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters /** Helper class for determining when two memories are equivalent while igoring * irrelevant details like name and info diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 3da4c391..131a198b 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -170,7 +170,7 @@ object VerilogMemDelays extends Pass { override def prerequisites = firrtl.stage.Forms.LowForm :+ Dependency(firrtl.passes.RemoveValidIf) - override val dependents = + override val optionalPrerequisiteOf = Seq( Dependency[VerilogEmitter], Dependency[SystemVerilogEmitter] ) diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 2a574f47..20fb1215 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -42,7 +42,7 @@ class WiringTransform extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters private val invalidates = Forms.VerilogOptimized.toSet -- Forms.MinimalHighForm override def invalidates(a: Transform): Boolean = invalidates(Dependency.fromTransform(a)) |